Sylvain Barraud

According to our database1, Sylvain Barraud authored at least 19 papers between 2011 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2021
Experimental Assessment of Variability in Junctionless Nanowire nMOS Transistors.
Proceedings of the 51st IEEE European Solid-State Device Research Conference, 2021

Wafer-scale fabrication of biologically sensitive Si nanowire FET: from pH sensing to electrical detection of DNA hybridization.
Proceedings of the 51st IEEE European Solid-State Device Research Conference, 2021

2019
Compact Analytical Model for Trap-Related Low Frequency Noise in Junctionless Transistors.
Proceedings of the 49th European Solid-State Device Research Conference, 2019

2018
Performance & reliability of 3D architectures (πfet, Finfet, Ωfet).
Proceedings of the IEEE International Reliability Physics Symposium, 2018

Si MOS technology for spin-based quantum computing.
Proceedings of the 48th European Solid-State Device Research Conference, 2018


2017
Harmonic distortion analysis of triple gate SOI nanowire MOSFETS down to 100 K.
Microelectron. Reliab., 2017

SOI CMOS technology for quantum information processing.
Proceedings of the 2017 IEEE International Conference on IC Design and Technology, 2017

A new method for junctionless transistors parameters extraction.
Proceedings of the 47th European Solid-State Device Research Conference, 2017

2016
Drain current model for short-channel triple gate junctionless nanowire transistors.
Microelectron. Reliab., 2016

Analog performance of strained SOI nanowires down to 10K.
Proceedings of the 46th European Solid-State Device Research Conference, 2016

Statistical characterization of drain current local and global variability in sub 15nm Si/SiGe Trigate pMOSFETs.
Proceedings of the 46th European Solid-State Device Research Conference, 2016

2015
Strain effect on mobility in nanowire MOSFETs down to 10nm width: Geometrical effects and piezoresistive model.
Proceedings of the 45th European Solid State Device Research Conference, 2015

Back-gate effects and detailed characterization of junctionless transistor.
Proceedings of the 45th European Solid State Device Research Conference, 2015

2013
Influence of device scaling on low-frequency noise in SOI tri-gate N- and p-type Si nanowire MOSFETs.
Proceedings of the European Solid-State Device Research Conference, 2013

Low-temperature transport characteristics in SOI and sSOI nanowires down to 8nm width: Evidence of IDS and mobility oscillations.
Proceedings of the European Solid-State Device Research Conference, 2013

2012
Study of carrier transport in strained and unstrained SOI tri-gate and omega-gate Si-nanowire MOSFETs.
Proceedings of the 2012 European Solid-State Device Research Conference, 2012

Scaling of Trigate nanowire (NW) MOSFETs Down to 5 nm Width: 300 K transition to Single Electron Transistor, challenges and opportunities.
Proceedings of the 2012 European Solid-State Device Research Conference, 2012

2011
Comparison of low-temperature electrical characteristics of gate-all-around nanowire FETs, Fin FETs and fully-depleted SOI FETs.
Microelectron. Reliab., 2011


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