Sangil Han

Orcid: 0009-0003-0153-3087

According to our database1, Sangil Han authored at least 17 papers between 2004 and 2026.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
Hierarchical vs. Flat Iteration in Shared-Weight Transformers.
CoRR, April, 2026

Graph partitioning-based matheuristic for residential waste collection problem with visual attractiveness and turn penalty.
Eur. J. Oper. Res., 2026

2025
Variable Selection and Basis Learning for Ordinal Classification.
J. Comput. Graph. Stat., 2025

Subspace Recovery in Winsorized PCA: Insights into Accuracy and Robustness.
Proceedings of the International Conference on Artificial Intelligence and Statistics, 2025

2024
A Design Framework for Cost-Efficient Sorters With Arbitrary Input/Output Constraints.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2024

Splitting of Composite Neural Networks via Proximal Operator With Information Bottleneck.
IEEE Access, 2024

Constrained Sorter Design using Zero-One Principle.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

Robust SVD Made Easy: A fast and reliable algorithm for large-scale data analysis.
Proceedings of the International Conference on Artificial Intelligence and Statistics, 2024

2021
Control the Information of the Image with Anisotropic Diffusion and Isotropic Diffusion for the Image Classification.
Proceedings of the Modern Management based on Big Data II and Machine Learning and Intelligent Systems III, 2021

2020

2009
Simulink<sup>®</sup>-based heterogeneous multiprocessor SoC design flow for mixed hardware/software refinement and simulation.
Integr., 2009

2007
Memory-efficient multithreaded code generation from Simulink for heterogeneous MPSoC.
Des. Autom. Embed. Syst., 2007

Reducing fine-grain communication overhead in multithread code generation for heterogeneous MPSoC.
Proceedings of the 10th International Workshop on Software and Compilers for Embedded Systems, 2007

Simulink-Based MPSoC Design Flow: Case Study of Motion-JPEG and H.264.
Proceedings of the 44th Design Automation Conference, 2007

2006
Buffer memory optimization for video codec application modeled in Simulink.
Proceedings of the 43rd Design Automation Conference, 2006

Functional modeling techniques for efficient SW code generation of video codec applications.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2004
An efficient scalable and flexible data transfer architecture for multiprocessor SoC with massive distributed memory.
Proceedings of the 41th Design Automation Conference, 2004


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