C. Mukherjee
Orcid: 0000-0002-8206-2779Affiliations:
- University of Bordeaux, Talence, France
According to our database1,
C. Mukherjee
authored at least 20 papers
between 2014 and 2023.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
-
on orcid.org
On csauthors.net:
Bibliography
2023
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023
SPICE Modeling in Verilog-A for Photo-Response in UTC-Photodiodes Targeting Beyond-5G Circuit Design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., September, 2023
Electrothermal modeling of junctionless vertical Si nanowire transistors for 3D logic circuit design.
Proceedings of the 53rd IEEE European Solid-State Device Research Conference, 2023
2022
Analysis of an Inverter Logic Cell based on 3D Vertical NanoWire Junction-Less Transistors.
Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022
Proceedings of the 20th IEEE Interregional NEWCAS Conference, 2022
Proceedings of the 52nd IEEE European Solid-State Device Research Conference, 2022
2021
Impact of Hot Carrier Degradation on the Performances of Current Mirrors based on a 55 nm BiCMOS Integrated Circuit Technology.
Proceedings of the 51st IEEE European Solid-State Device Research Conference, 2021
Electro-Thermal Limitations and Device Degradation of SiGe HBTs with Emphasis on Circuit Performance.
Proceedings of the IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium, 2021
InP DHBT Characterization up to 500 GHz and Compact Model Validation Towards THz Circuit Design.
Proceedings of the IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium, 2021
0.4-μm InP/InGaAs DHBT with a 380-GHz ${f_{T}}$, > 600-GHz $f_{\max}$ and BVCE0 > 4.5 V.
Proceedings of the IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium, 2021
2020
3D logic cells design and results based on Vertical NWFET technology including tied compact model.
CoRR, 2020
3D Logic Cells Design and Results Based on Vertical NWFET Technology Including Tied Compact Model.
Proceedings of the 28th IFIP/IEEE International Conference on Very Large Scale Integration, 2020
2019
First Uni-Traveling Carrier Photodiode Compact Model Enabling Future Terahertz Communication System Design.
Proceedings of the 49th European Solid-State Device Research Conference, 2019
2017
Microelectron. Reliab., 2017
Proceedings of the 47th European Solid-State Device Research Conference, 2017
2016
Comprehensive study of random telegraph noise in base and collector of advanced SiGe HBT: Bias, geometry and trap locations.
Proceedings of the 46th European Solid-State Device Research Conference, 2016
Proceedings of the 46th European Solid-State Device Research Conference, 2016
2015
Proceedings of the 45th European Solid State Device Research Conference, 2015
Proceedings of the 45th European Solid State Device Research Conference, 2015
2014
Qualitative assessment of epitaxial graphene FETs on SiC substrates via pulsed measurements and temperature variation.
Proceedings of the 44th European Solid State Device Research Conference, 2014