C. Mukherjee

According to our database1, C. Mukherjee authored at least 9 papers between 2014 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

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On csauthors.net:

Bibliography

2020
3D logic cells design and results based on Vertical NWFET technology including tied compact model.
CoRR, 2020

2019
First Uni-Traveling Carrier Photodiode Compact Model Enabling Future Terahertz Communication System Design.
Proceedings of the 49th European Solid-State Device Research Conference, 2019

2017
Random telegraph noise in SiGe HBTs: Reliability analysis close to SOA limit.
Microelectron. Reliab., 2017

1/f Noise in 3D vertical gate-all-around junction-less silicon nanowire transistors.
Proceedings of the 47th European Solid-State Device Research Conference, 2017

2016
Comprehensive study of random telegraph noise in base and collector of advanced SiGe HBT: Bias, geometry and trap locations.
Proceedings of the 46th European Solid-State Device Research Conference, 2016

Physics-based electrical compact model for monolayer Graphene FETs.
Proceedings of the 46th European Solid-State Device Research Conference, 2016

2015
Characterization and modeling of low-frequency noise in CVD-grown graphene FETs.
Proceedings of the 45th European Solid State Device Research Conference, 2015

A new physics-based compact model for Bilayer Graphene Field-Effect Transistors.
Proceedings of the 45th European Solid State Device Research Conference, 2015

2014
Qualitative assessment of epitaxial graphene FETs on SiC substrates via pulsed measurements and temperature variation.
Proceedings of the 44th European Solid State Device Research Conference, 2014


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