Carlos Ornelas

According to our database1, Carlos Ornelas authored at least 3 papers between 2012 and 2013.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2013
A Digital Fractional-N PLL With a PVT and Mismatch Insensitive TDC Utilizing Equivalent Time Sampling Technique.
IEEE J. Solid State Circuits, 2013

2012
A reconfigurable distributed all-digital clock generator core with SSC and skew correction in 22nm high-k tri-gate LP CMOS.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A digital fractional-N PLL with a 3mW 0.004mm<sup>2</sup> 6-bit PVT and mismatch insensitive TDC.
Proceedings of the 38th European Solid-State Circuit conference, 2012


  Loading...