Satish Yada

According to our database, Satish Yada authored at least 10 papers between 2007 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2022

Design Methodology for Scalable 2.5D/3D Heterogenous Tiled Chiplet Systems.

Srivatsa Rangachar Srinivasa, Jainaveen Sundaram Priya, Dileep Kurian, Erika Ramirez Lozano, Satish Yada, Saransh Chhabra, Kamakhya Prasad Sahu, Paolo A. Aseron, Ronald Kalim, Anuradha Srinivasan, Tanay Karnik

Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022

Resonant Rotary Clock Synchronization with Active and Passive Silicon Interposer.

Ragh Kuttappa, Baris Taskin, Vinayak Honkote, Satish Yada, Jainaveen Sundaram, Dileep Kurian, Tanay Karnik, Anuradha Srinivasan

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2020

A 0.05pJ/Pixel 70fps FHD 1Meps Event-Driven Visual Data Processing Unit.

Somnath Paul, Turbo Majumder, Charles Augustine, Andres F. Malavasi, S. Usirikayala, Raghavan Kumar, Jisna Kollikunnel, S. Chhabra, Satish Yada, M. L. Barajas, C. Ornelas, Dan Lake, Muhammad M. Khellah, Jim Tschanz, Vivek De

Proceedings of the IEEE Symposium on VLSI Circuits, 2020

2019

A Distributed Autonomous and Collaborative Multi-Robot System Featuring a Low-Power Robot SoC in 22nm CMOS for Integrated Battery-Powered Minibots.

Vinayak Honkote, Dileep Kurian, Sriram Muthukumar, Dibyendu Ghosh, Satish Yada, Kartik Jain, Bradley Jackson, Ilya Klotchkov, Mallikarjuna Rao Nimmagadda, Shreela Dattawadkar, Pranjali Deshmukh, Ankit Gupta, Jaykant Timbadiya, Ravi Pali, Karthik Narayanan, Saksham Soni, Saransh Chhabra, Praveen Dhama, N. Sreenivasulu, Jisna Kollikunnel, Sureshbabu Kadavakollu, Vijay Deepak Sivaraj, Paolo A. Aseron, Leonid Azarenkov, Nancy Robinson, Arun Radhakrishnan, Mikhail J. Moiseev, Ganeshram Nandakumar, Akhila Madhukumar, Roman Popov, Kamakhya P. Sahu, Ramesh Peguvandla, Alberto Del Rio Ruiz, Mukesh Bhartiya, Anuradha Srinivasan, Vivek De

Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2018

A cm-scale self-powered intelligent and secure IoT edge mote featuring an ultra-low-power SoC in 14nm tri-gate CMOS.

Tanay Karnik, Dileep Kurian, Paolo A. Aseron, Richard Dorrance, Erkan Alpman, Angela Nicoara, Roman Popov, Leonid Azarenkov, Mikhail J. Moiseev, Li Zhao, Santosh Ghosh, Rafael Misoczki, Ankit Gupta, M. Akhila, Sriram Muthukumar, Saurabh Bhandari, Satish Yada, Kartik Jain, Robert Flory, Chanitnan Kanthapanit, Eduardo Quijano, Bradley Jackson, Hao Luo, Suhwan Kim, Vaibhav A. Vaidya, Adel Elsherbini, Renzhi Liu, Farhana Sheikh, Omesh Tickoo, Ilya Klotchkov, Manoj R. Sastry, Sheldon Sun, Mukesh Bhartiya, Anuradha Srinivasan, Yatin Hoskote, Hong Wang, Vivek De

Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2012

A Reconfigurable On-die Traffic Generator in 45nm CMOS for a 48 iA-32 Core Network-on-Chip.

Praveen Salihundam, Mohammed Asadullah Khan, Shailendra Jain, Yatin Vasant Hoskote, Satish Yada, Shasi Kumar, Vasantha Erraguntla, Sriram R. Vangal, Nitin Borkar

Proceedings of the 25th International Conference on VLSI Design, 2012

A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS.

Shailendra Jain, Surhud Khare, Satish Yada, V. Ambili, Praveen Salihundam, Shiva Ramani, Sriram Muthukumar, M. Srinivasan, Arun Kumar, Shasi Kumar, Rajaraman Ramanarayanan, Vasantha Erraguntla, Jason Howard, Sriram R. Vangal, Saurabh Dighe, Gregory Ruhl, Paolo A. Aseron, Howard Wilson, Nitin Borkar, Vivek De, Shekhar Borkar

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

An IA-32 processor with a wide voltage operating range in 32nm CMOS.

Gregory Ruhl, Saurabh Dighe, Shailendra Jain, Surhud Khare, Satish Yada, V. Ambili, Praveen Salihundam, Shiva Ramani, Sriram Muthukumar, M. Srinivasan, Arun Kumar, Shasi Kumar, Rajaraman Ramanarayanan, Vasantha Erraguntla, Jason Howard, Sriram R. Vangal, Paolo A. Aseron, Howard Wilson, Nitin Borkar

Proceedings of the 2012 IEEE Hot Chips 24 Symposium (HCS), 2012

2010

A 48-Core IA-32 message-passing processor with DVFS in 45nm CMOS.

Jason Howard, Saurabh Dighe, Yatin Vasant Hoskote, Sriram R. Vangal, David Finan, Gregory Ruhl, David Jenkins, Howard Wilson, Nitin Borkar, Gerhard Schrom, Fabric Pailet, Shailendra Jain, Tiju Jacob, Satish Yada, Sraven Marella, Praveen Salihundam, Vasantha Erraguntla, Michael Konow, Michael Riepen, Guido Droege, Joerg Lindemann, Matthias Gries, Thomas Apel, Kersten Henriss, Tor Lund-Larsen, Sebastian Steibl, Shekhar Borkar, Vivek De, Rob F. Van der Wijngaart, Timothy G. Mattson

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2007

Modified Stability Checking for On-line Error Detection.

Satish Yada, Bharadwaj S. Amrutur, Rubin A. Parekhji

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007