Krishnamurthy Soumyanath

According to our database1, Krishnamurthy Soumyanath authored at least 28 papers between 1990 and 2013.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2013
A 32 nm SoC With Dual Core ATOM Processor and RF WiFi Transceiver.
IEEE J. Solid State Circuits, 2013

2012
A reconfigurable distributed all-digital clock generator core with SSC and skew correction in 22nm high-k tri-gate LP CMOS.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012


2011
A Flip-Chip-Packaged 25.3 dBm Class-D Outphasing Power Amplifier in 32 nm CMOS for WLAN Application.
IEEE J. Solid State Circuits, 2011

A 2.5GHz 32nm 0.35mm<sup>2</sup> 3.5dB NF -5dBm P1dB fully differential CMOS push-pull LNA with integrated 34dBm T/R switch and ESD protection.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2010
A highly linear 25dBm outphasing power amplifier in 32nm CMOS for WLAN application.
Proceedings of the 36th European Solid-State Circuits Conference, 2010

2009
A Class-E PA With Pulse-Width and Pulse-Position Modulation in 65 nm CMOS.
IEEE J. Solid State Circuits, 2009

A 1.05 V 1.6 mW, 0.45°C 3σ Resolution ΣΔ Based Temperature Sensor With Parasitic Resistance Compensation in 32 nm Digital CMOS Process.
IEEE J. Solid State Circuits, 2009

A 1.05V 1.6mW 0.45°C 3σ-resolution ΔΣ-based temperature sensor with parasitic-resistance compensation in 32nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

A 1.1V 50mW 2.5GS/s 7b Time-Interleaved C-2C SAR ADC in 45nm LP digital CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

A 630μW zero-crossing-based ΔΣ ADC using switched-resistor current sources in 45nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2008
Desensitized CMOS Low-Noise Amplifiers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008

A 64 GHz LNA With 15.5 dB Gain and 6.5 dB NF in 90 nm CMOS.
IEEE J. Solid State Circuits, 2008

A 28.6dBm 65nm Class-E PA with Envelope Restoration by Pulse-Width and Pulse-Position Modulation.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

A 28mW Spectrum-Sensing Reconfigurable 20MHz 72dB-SNR 70dB-SNDR DT ΔΣ ADC for 802.11n/WiMAX Receivers.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

A 3.6GHz, 16mW ΣΔ DAC for a 802.11n / 802.16e transmitter with 30dB digital power control in 90nm CMOS.
Proceedings of the ESSCIRC 2008, 2008

A 1.7-GHz 1.5-mW digitally-controlled FBAR oscillator with 0.03-ppb resolution.
Proceedings of the ESSCIRC 2008, 2008

2006
A 5GHz 108Mb/s 2x2 MIMO Transceiver with Fully Integrated +16dBm PAs in 90nm CMOS.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2005
A 5 GHz class-AB power amplifier in 90 nm CMOS with digitally-assisted AM-PM correction.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

A 90-nm MOS-only 3-11GHz transmitter for UWB.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2004
Desensitized design of MOS low noise amplifiers by R<sub>n</sub> minimization.
Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004

8 GHz, 20mW, fast locking, fractional-N frequency synthesizer with optimized 3<sup>rd</sup> order, 3/5-bit IIR and 3<sup>rd</sup> order 3-bit-FIR noise shapers in 90nm CMOS.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

Measurement and modeling of noise parameters for desensitized low noise amplifiers.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2001
A low-leakage dynamic multi-ported register file in 0.13mm CMOS.
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

Leakage control and tolerance challenges for sub-0.1µm microprocessor circuits.
Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, 2001

2000
Multiple-parameter CMOS IC testing with increased sensitivity for I_DDQ.
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

Reliable low-power design in the presence of deep submicron noise (embedded tutorial session).
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000

1990
An analog parallel distributed solution to the shortest path problem.
Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1990


  Loading...