Catherine H. Gebotys
Orcid: 0000-0002-7835-3741Affiliations:
- University of Waterloo, Canada
  According to our database1,
  Catherine H. Gebotys
  authored at least 82 papers
  between 1988 and 2021.
  
  
Collaborative distances:
Collaborative distances:
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Online presence:
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    on orcid.org
On csauthors.net:
Bibliography
  2021
    Cryptogr. Commun., 2021
    
  
  2020
Analysis of Dynamic Laser Injection and Quiescent Photon Emissions on an Embedded Processor.
    
  
    J. Hardw. Syst. Secur., 2020
    
  
    Proceedings of the 21st International Symposium on Quality Electronic Design, 2020
    
  
Going Deep: Using deep learning techniques with simplified mathematical models against XOR BR and TBR PUFs (Attacks and Countermeasures).
    
  
    Proceedings of the 2020 IEEE International Symposium on Hardware Oriented Security and Trust, 2020
    
  
  2019
    Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019
    
  
    Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
    
  
PUFs Deep Attacks: Enhanced modeling attacks using deep learning techniques to break the security of double arbiter PUFs.
    
  
    Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
    
  
  2018
    Proceedings of the Principles and Practice of Constraint Programming, 2018
    
  
  2017
    Proceedings of the Verified Software. Theories, Tools, and Experiments, 2017
    
  
    Proceedings of the Theory and Applications of Satisfiability Testing - SAT 2017 - 20th International Conference, Melbourne, VIC, Australia, August 28, 2017
    
  
  2016
    ACM Trans. Embed. Comput. Syst., 2016
    
  
  2015
A Sliding Window Phase-Only Correlation Method for Side-Channel Alignment in a Smartphone.
    
  
    ACM Trans. Embed. Comput. Syst., 2015
    
  
  2013
A Quantitative Analysis of a Novel SEU-Resistant SHA-2 and HMAC Architecture for Space Missions Security.
    
  
    IEEE Trans. Aerosp. Electron. Syst., 2013
    
  
  2011
    Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
    
  
    Proceedings of the Advances in Cryptology - EUROCRYPT 2011, 2011
    
  
  2010
    ACM Trans. Reconfigurable Technol. Syst., 2010
    
  
Analysis of Efficient Techniques for Fast Elliptic Curve Cryptography on x86-64 based Processors.
    
  
    IACR Cryptol. ePrint Arch., 2010
    
  
    Proceedings of the Cryptographic Hardware and Embedded Systems, 2010
    
  
    Proceedings of the 5th Workshop on Embedded Systems Security, 2010
    
  
  2009
Hardware Mechanisms for Memory Authentication: A Survey of Existing Techniques and Engines.
    
  
    Trans. Comput. Sci., 2009
    
  
Tailoring a Reconfigurable Platform to SHA-256 and HMAC through Custom Instructions and Peripherals.
    
  
    Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009
    
  
Efficient Technique for the FPGA Implementation of the AES MixColumns Transformation.
    
  
    Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009
    
  
Fast Multibase Methods and Other Several Optimizations for Elliptic Curve Scalar Multiplication.
    
  
    Proceedings of the Public Key Cryptography, 2009
    
  
    Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009
    
  
    Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009
    
  
    Proceedings of the Applied Cryptography and Network Security, 7th International Conference, 2009
    
  
  2008
Setting Speed Records with the (Fractional) Multibase Non-Adjacent Form Method for Efficient Elliptic Curve Scalar Multiplication.
    
  
    IACR Cryptol. ePrint Arch., 2008
    
  
    Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008
    
  
An Approach for Recovering Satellites and their Cryptographic Capabilities in the Presence of SEUs and Attacks.
    
  
    Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, 2008
    
  
  2007
Enhanced Current-Balanced Logic (ECBL): An Area Efficient Solution to Secure Smart Cards against Differential Power Attack.
    
  
    Proceedings of the Fourth International Conference on Information Technology: New Generations (ITNG 2007), 2007
    
  
    Proceedings of the Fourth International Conference on Information Technology: New Generations (ITNG 2007), 2007
    
  
  2006
    IEEE Trans. Very Large Scale Integr. Syst., 2006
    
  
    ACM Trans. Embed. Comput. Syst., 2006
    
  
    Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006
    
  
  2005
    ACM Trans. Embed. Comput. Syst., 2005
    
  
    Proceedings of the NETWORKING 2005: Networking Technologies, 2005
    
  
    Proceedings of the International Symposium on Information Technology: Coding and Computing (ITCC 2005), 2005
    
  
    Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2005, 7th International Workshop, Edinburgh, UK, August 29, 2005
    
  
  2004
Design of secure cryptography against the threat of power-attacks in DSP-embedded processors.
    
  
    ACM Trans. Embed. Comput. Syst., 2004
    
  
    Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004
    
  
Secure and safety-critical vs. insecure, non safety-critical embedded systems: do they require completely different design approaches?
    
  
    Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004
    
  
    Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004
    
  
  2003
    Proceedings of the 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), 2003
    
  
    Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2003
    
  
  2002
A network flow approach to memory bandwidth utilization in embedded DSP core processors.
    
  
    IEEE Trans. Very Large Scale Integr. Syst., 2002
    
  
    Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002
    
  
    Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002
    
  
Secure Elliptic Curve Implementations: An Analysis of Resistance to Power-Attacks in a DSP Processor.
    
  
    Proceedings of the Cryptographic Hardware and Embedded Systems, 2002
    
  
  2001
Current consumption dynamics at instruction and program level for a <i>VLIW</i> DSP processor.
    
  
    Proceedings of the 14th International Symposium on Systems Synthesis, 2001
    
  
Modeling Power Dynamics for an Embedded DSP Processor Core. An Empirical Model.
  
    Proceedings of the SOC Design Methodologies, 2001
    
  
    Proceedings of the 38th Design Automation Conference, 2001
    
  
  2000
    Proceedings of the 37th Conference on Design Automation, 2000
    
  
  1999
    IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999
    
  
Statistically based prediction of power dissipation for complex embedded DSP processors.
    
  
    Microprocess. Microsystems, 1999
    
  
    Proceedings of the 32nd Annual Hawaii International Conference on System Sciences (HICSS-32), 1999
    
  
  1998
Optimizing Energy During Systems Synthesis of Computer Intensive Realtime Applications.
    
  
    VLSI Design, 1998
    
  
    Integr. Comput. Aided Eng., 1998
    
  
An empirical comparison of algorithmic, instruction, and architectural power prediction models for high performance embedded DSP processors.
    
  
    Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998
    
  
Complexities in DSP Software Compilation: Performance, Code Size Power, Retargetability.
    
  
    Proceedings of the Thirty-First Annual Hawaii International Conference on System Sciences, 1998
    
  
  1997
An Efficient Model for DSP Code Generation: Performance, Code Size, Estimated Energy.
    
  
    Proceedings of the 10th International Symposium on System Synthesis, 1997
    
  
    Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997
    
  
    Proceedings of the 30th Annual Hawaii International Conference on System Sciences (HICSS-30), 1997
    
  
    Proceedings of the 34st Conference on Design Automation, 1997
    
  
  1996
    Proceedings of the 29th Annual Hawaii International Conference on System Sciences (HICSS-29), 1996
    
  
  1995
    J. VLSI Signal Process., 1995
    
  
    Proceedings of the 28th Annual Hawaii International Conference on System Sciences (HICSS-28), 1995
    
  
  1994
    IEEE Trans. Very Large Scale Integr. Syst., 1994
    
  
    Proceedings of the 27th Annual Hawaii International Conference on System Sciences (HICSS-27), 1994
    
  
  1993
    IEEE J. Solid State Circuits, March, 1993
    
  
    IEEE Trans. Very Large Scale Integr. Syst., 1993
    
  
  1992
    IEEE J. Solid State Circuits, March, 1992
    
  
    Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992
    
  
    Proceedings of the 29th Design Automation Conference, 1992
    
  
  1991
Simultaneous Scheduling and Allocation for Cost Constrained Optimal Architectural Synthesis.
    
  
    Proceedings of the 28th Design Automation Conference, 1991
    
  
  1990
    Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990
    
  
  1989
    IEEE J. Solid State Circuits, April, 1989
    
  
  1988
    Proceedings of the Computer Design: VLSI in Computers and Processors, 1988
    
  
    Proceedings of the 25th ACM/IEEE Conference on Design Automation, 1988