Peter Marwedel

According to our database1, Peter Marwedel authored at least 166 papers between 1979 and 2019.

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Awards

IEEE Fellow

IEEE Fellow 2010, "For contributions to compilation techniques and embedded system design".

Timeline

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Bibliography

2019
Can Flexible Multi-Core Scheduling Help to Execute Machine Learning Algorithms Resource-Efficiently?
Proceedings of the 22nd International Workshop on Software and Compilers for Embedded Systems, 2019

2017
Memory-Aware Optimization of Embedded Software for Multiple Objectives.
Proceedings of the Handbook of Hardware/Software Codesign., 2017

Parallelism analysis: Precise WCET values for complex multi-core systems.
Sci. Comput. Program., 2017

A parallelization approach for resource-restricted embedded heterogeneous MPSoCs inspired by OpenMP.
Journal of Systems and Software, 2017

RAMBO: Resource-Aware Model-Based Optimization with Scheduling for Heterogeneous Runtimes and a Comparison with Asynchronous Model-Based Optimization.
Proceedings of the Learning and Intelligent Optimization - 11th International Conference, 2017

Quality Evaluation Strategies for Approximate Computing in Embedded Systems.
Proceedings of the Technological Innovation for Smart Systems, 2017

2016
mmapcopy: efficient memory footprint reduction using application knowledge.
Proceedings of the 31st Annual ACM Symposium on Applied Computing, 2016

Faster Model-Based Optimization Through Resource-Aware Scheduling Strategies.
Proceedings of the Learning and Intelligent Optimization - 10th International Conference, 2016

Compensate or ignore? meeting control robustness requirements through adaptive soft-error handling.
Proceedings of the 17th ACM SIGPLAN/SIGBED Conference on Languages, 2016

Cyber-Physical Systems: Opportunities, Challenges and (Some) Solutions.
Proceedings of the Management of Cyber Physical Objects in the Future Internet of Things, 2016

2015
Multi-layer software reliability for unreliable hardware.
it - Information Technology, 2015

Plasmon-based Virus Detection on Heterogeneous Embedded Systems.
Proceedings of the 18th International Workshop on Software and Compilers for Embedded Systems, 2015

2014
Building timing predictable embedded systems.
ACM Trans. Embedded Comput. Syst., 2014

A Unified WCET analysis framework for multicore platforms.
ACM Trans. Embedded Comput. Syst., 2014

Static analysis of multi-core TDMA resource arbitration delays.
Real-Time Systems, 2014

Multi-objective, Energy-Aware GPGPU Design Space Exploration for Medical or Industrial Applications.
Proceedings of the Tenth International Conference on Signal-Image Technology and Internet-Based Systems, 2014

WCET-aware scheduling optimizations for multi-core real-time systems.
Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014

Static WCET analysis of the H.264/AVC decoder exploiting coding information.
Proceedings of the 2014 IEEE 20th International Conference on Embedded and Real-Time Computing Systems and Applications, 2014

Multi-objective computation offloading for mobile biosensors via LTE.
Proceedings of the 4th International Conference on Wireless Mobile Communication and Healthcare: "Transforming healthcare through innovations in mobile and wireless technologies", 2014

Flipped classroom teaching for a cyber-physical system course - An adequate presence-based learning approach in the internet age.
Proceedings of the 10th European Workshop on Microelectronics Education (EWME), 2014

Computing maximum blocking times with explicit path analysis under non-local flow bounds.
Proceedings of the 2014 International Conference on Embedded Software, 2014

Dynamic page sharing optimization for the R language.
Proceedings of the DLS'14, 2014

A context-aware battery lifetime model for carrier aggregation enabled LTE-A systems.
Proceedings of the 11th IEEE Consumer Communications and Networking Conference, 2014

Modellierung und Optimierung eines Biosensors zur Detektion viraler Strukturen.
Proceedings of the Bildverarbeitung für die Medizin 2014, Algorithmen - Systeme, 2014

Introduction: Modeling, Analysis and Synthesis of Embedded Software and Systems.
Proceedings of the Embedded Systems Development, From Functional Models to Implementations, 2014

2013
Improving the fault resilience of an H.264 decoder using static analysis methods.
ACM Trans. Embedded Comput. Syst., 2013

A survey of cross-layer power-reliability tradeoffs in multi and many core systems-on-chip.
Microprocessors and Microsystems - Embedded Hardware Design, 2013

Evaluation of resource arbitration methods for multi-core real-time systems.
Proceedings of the 13th International Workshop on Worst-Case Execution Time Analysis, 2013

Automatic Extraction of Task-Level Parallelism for Heterogeneous MPSoCs.
Proceedings of the 42nd International Conference on Parallel Processing, 2013

Fast and Low-Cost Instruction-Aware Fault Injection.
Proceedings of the Informatik 2013, 2013

Simple analysis of partial worst-case execution paths on general control flow graphs.
Proceedings of the International Conference on Embedded Software, 2013

Automatic Extraction of pipeline parallelism for embedded heterogeneous multi-core platforms.
Proceedings of the International Conference on Compilers, 2013

2012
Introduction to the Special Section on SCOPES'09.
ACM Trans. Embedded Comput. Syst., 2012

Energy Efficiency in IT.
it - Information Technology, 2012

Design space exploration towards a realtime and energy-aware GPGPU-based analysis of biosensor data.
Computer Science - R&D, 2012

Efficient computing in cyber-physical systems.
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012

A Unified WCET Analysis Framework for Multi-core Platforms.
Proceedings of the 2012 IEEE 18th Real Time and Embedded Technology and Applications Symposium, 2012

Efficient Resource Management based on Non-Functional Requirements for Sensor/Actuator Networks.
Proceedings of the Ninth International Network Conference (INC 2012), 2012

Feedback-Based Global Instruction Scheduling for GPGPU Applications.
Proceedings of the Computational Science and Its Applications - ICCSA 2012, 2012

MAMOT: Memory-Aware Mapping Optimization Tool for MPSoC.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Multi-objective aware extraction of task-level parallelism using genetic algorithms.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

ILP-based Memory-Aware Mapping Optimization for MPSoCs.
Proceedings of the 15th IEEE International Conference on Computational Science and Engineering, 2012

Automatic extraction of multi-objective aware pipeline parallelism using genetic algorithms.
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

WCET-aware static locking of instruction caches.
Proceedings of the 10th Annual IEEE/ACM International Symposium on Code Generation and Optimization, 2012

Reconciling Compilation and Timing Analysis.
Proceedings of the Advances in Real-Time Systems (to Georg Färber on the occasion of his appointment as Professor Emeritus at TU München after leading the Lehrstuhl für Realzeit-Computersysteme for 34 illustrious years)., 2012

Classification-Based Improvement of Application Robustness and Quality of Service in Probabilistic Computer Systems.
Proceedings of the Architecture of Computing Systems - ARCS 2012 - 25th International Conference, Munich, Germany, February 28, 2012

2011
Approximating Pareto optimal compiler optimization sequences - a trade-off between WCET, ACET and code size.
Softw., Pract. Exper., 2011

Automatic Extraction of Pipeline Parallelism for Embedded Software Using Linear Programming.
Proceedings of the 17th IEEE International Conference on Parallel and Distributed Systems, 2011

Unreliable yet useful - reliability annotations for data in cyber-physical systems.
Proceedings of the Informatik 2011: Informatik schafft Communities, 2011

Embedded system design 2.0: rationale behind a textbook revision.
Proceedings of the 6th Workshop on Embedded Systems Education, 2011

A synergetic approach to accurate analysis of cache-related preemption delay.
Proceedings of the 11th International Conference on Embedded Software, 2011

Bus-Aware Multicore WCET Analysis through TDMA Offset Bounds.
Proceedings of the 23rd Euromicro Conference on Real-Time Systems, 2011

Mapping of applications to MPSoCs.
Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011


WCET-driven branch prediction aware code positioning.
Proceedings of the 14th International Conference on Compilers, 2011

GPGPU-basierte Echtzeitdetektion von Nanoobjekten mittels Plasmonen-unterstützter Mikroskopie.
Proceedings of the Bildverarbeitung für die Medizin 2011: Algorithmen - Systeme, 2011

Embedded System Design - Embedded Systems Foundations of Cyber-Physical Systems, Second Edition.
Embedded Systems, Springer, ISBN: 978-94-007-0256-1, 2011

Worst-Case Execution Time Aware Compilation Techniques for Real-Time Systems.
Springer, ISBN: 978-90-481-9928-0, 2011

2010
An automatic framework for dynamic data structures optimization in C.
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

Versatile system-level memory-aware platform description approach for embedded MPSoCs.
Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, 2010

Mapping Embedded Applications on MPSoCs: The MNEMEE Approach.
Proceedings of the VLSI 2010 Annual Symposium - Selected papers, 2010

WCET-Driven Cache-Aware Memory Content Selection.
Proceedings of the 13th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing, 2010

Multi-objective Exploration of Compiler Optimizations for Real-Time Systems.
Proceedings of the 13th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing, 2010

Improving transient memory fault resilience of an H.264 decoder.
Proceedings of the 8th IEEE Workshop on Embedded Systems for Real-Time Multimedia, 2010

Automatic parallelization of embedded software using hierarchical task graphs and integer linear programming.
Proceedings of the 8th International Conference on Hardware/Software Codesign and System Synthesis, 2010

MNEMEE: a framework for memory management and optimization of static and dynamic data in MPSoCs.
Proceedings of the 2010 International Conference on Compilers, 2010

Plasmonen-unterstützte Mikroskopie zur Detektion von Viren.
Proceedings of the Bildverarbeitung für die Medizin 2010 - Algorithmen - Systeme, 2010

Plea for a Holistic Analysis of the Relationship between Information Technology and Carbon-Dioxide Emissions.
Proceedings of the ARCS '10, 2010

Superblock-Based Source Code Optimizations for WCET Reduction.
Proceedings of the 10th IEEE International Conference on Computer and Information Technology, 2010

2009
WCET-aware Software Based Cache Partitioning for Multi-Task Real-Time Systems.
Proceedings of the 9th Intl. Workshop on Worst-Case Execution Time Analysis, 2009

Accelerating WCET-driven optimizations by the invariant path paradigm: a case study of loop unswitching.
Proceedings of the 12th International Workshop on Software and Compilers for Embedded Systems, 2009

Plädoyer für eine ganzheitliche Betrachtung des Zusammenhangs zwischen Informationstechnologie und CO2-Produktion.
Proceedings of the Informatik 2009: Im Focus das Leben, 2009

Combining Worst-Case Timing Models, Loop Unrolling, and Static Loop Analysis for WCET Minimization.
Proceedings of the 21st Euromicro Conference on Real-Time Systems, 2009

Dynamic web service orchestration applied to the device profile for web services in hierarchical networks.
Proceedings of the 4th International Conference on COMmunication System softWAre and MiddlewaRE (COMSWARE 2009), 2009

A Fast and Precise Static Loop Analysis Based on Abstract Interpretation, Program Slicing and Polytope Models.
Proceedings of the CGO 2009, 2009

2008
WCET-driven, code-size critical procedure cloning.
Proceedings of the 11th International Workshop on Software and Compilers for Embedded Systems, 2008

WCET-driven Cache-based Procedure Positioning Optimizations.
Proceedings of the 20th Euromicro Conference on Real-Time Systems, 2008

Eingebettete Systeme (korrigierter Nachdruck).
eXamen.press, Springer, ISBN: 978-3-540-34048-5, 2008

2007
Operating system integrated energy aware scratchpad allocation strategies for multiprocess applications.
Proceedings of the 10th International Workshop on Software and Compilers for Embedded Systems, 2007

Influence of procedure cloning on WCET prediction.
Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007

Advanced memory optimization techniques for low-power embedded processors.
Springer, ISBN: 978-1-4020-5896-7, 2007

2006
Overlay techniques for scratchpad memories in low power embedded processors.
IEEE Trans. VLSI Syst., 2006

Cache-Aware Scratchpad-Allocation Algorithms for Energy-Constrained Embedded Systems.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Compilation and Simulation Tool Chain for Memory Aware Energy Optimizations .
Proceedings of the Embedded Computer Systems: Architectures, 2006

Fast, efficient and predictable memory accesses - optimization algorithms for memory architecture aware compilation.
Kluwer, ISBN: 978-1-4020-4821-0, 2006

2005
Towards laying common grounds for embedded system design education.
SIGBED Review, 2005

Memory Optimization Techniques for Low-Power Embedded Processors.
Proceedings of the INFORMATIK 2005, 2005

Scratchpad Sharing Strategies for Multiprocess Embedded Systems: A First Approach.
Proceedings of the 2005 3rd Workshop on Embedded Systems for Real-Time Multimedia, 2005

Influence of Memory Hierarchies on Predictability for Time Constrained Embedded Software.
Proceedings of the 2005 Design, 2005

What will system level design be when it grows up?
Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005

2004
Compiler-optimized usage of partitioned memories.
Proceedings of the 3rd Workshop on Memory Performance Issues, 2004

Bridges to computer architecture education.
Proceedings of the 2004 workshop on Computer architecture education, 2004

Cache-Aware Scratchpad Allocation Algorithm.
Proceedings of the 2004 Design, 2004

Phase Coupled Code Generation for DSPs Using a Genetic Algorithm.
Proceedings of the 2004 Design, 2004

Fast, predictable and low energy memory references through architecture-aware compilation.
Proceedings of the Perspectives Workshop: Design of Systems with Predictable Behaviour, 2004

Dynamic overlay of scratchpad memory for energy minimization.
Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004

Embedded systems education: how to teach the required skills?
Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004

Secure and safety-critical vs. insecure, non safety-critical embedded systems: do they require completely different design approaches?
Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004

Compiler based exploration of DSP energy savings by SIMD operations.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

Source code optimization techniques for data flow dominated embedded software.
Kluwer, ISBN: 978-1-4020-2822-9, 2004

2003
Multimedia components for the visualization of dynamic behavior in computer architectures.
Proceedings of the 2003 workshop on Computer architecture education, 2003

Efficient Scratchpad Allocation Algorithms for Energy Constrained Embedded Systems.
Proceedings of the Power-Aware Computer Systems, Third International Workshop, 2003

Overcoming The Limitations of Traditional Media For Teaching Modern Processor Desing.
Proceedings of the 2003 International Conference on Microelectronics Systems Education, 2003

Control Flow Driven Splitting of Loop Nests at the Source Code Level .
Proceedings of the 2003 Design, 2003

Data partitioning for maximal scratchpad usage.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

Control Flow Driven Splitting of Loop Nests at the Source Code Level.
Proceedings of the Embedded Software for SoC, 2003

Embedded system design.
Kluwer, ISBN: 978-1-4020-7690-9, 2003

2002
Guest Editor's Introduction: Processor-Based Designs.
IEEE Design & Test of Computers, 2002

Reducing Energy Consumption by Dynamic Copying of Instructions onto Onchip Memory.
Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002

Embedded Software: How To Make It Efficient?
Proceedings of the 2002 Euromicro Symposium on Digital Systems Design (DSD 2002), 2002

Assigning Program and Data Objects to Scratchpad for Energy Reduction.
Proceedings of the 2002 Design, 2002

Scratchpad memory: design alternative for cache on-chip memory in embedded systems.
Proceedings of the Tenth International Symposium on Hardware/Software Codesign, 2002

2001
Analysis of the influence of register file size on energyconsumption, code size, and execution time.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2001

Guest editorial.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2001

Compiler für eingebettete Prozessoren (Compilers for Embedded Processors).
it+ti - Informationstechnik und Technische Informatik, 2001

Low-Energy DSP Code Generation Using a Genetic Algorithm.
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

Evaluating register file size in ASIP design.
Proceedings of the Ninth International Symposium on Hardware/Software Codesign, 2001

Optimized address assignment for DSPs with SIMD memory accesses.
Proceedings of ASP-DAC 2001, 2001

Retargetable compiler technology for embedded systems - tools and applications.
Kluwer, ISBN: 978-0-7923-7578-4, 2001

2000
Eingebettete Systeme.
LOG IN, 2000

1999
Array Index Allocation under Register Constraints in DSP Programs.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Function inlining under code size constraints for embedded processors.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

1998
Retargetable Code Generation Based on Structural Processor Description.
Design Autom. for Emb. Sys., 1998

Interface Synthesis for Embedded Applications in a Co Design Environment.
Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

Synthesis of Communicating Controllers for Concurrent Hardware/Software Systems.
Proceedings of the 1998 Design, 1998

Register-Constrained Address Computation in DSP Programs.
Proceedings of the 1998 Design, 1998

Optimized Array Index Computation in DSP Programs.
Proceedings of the ASP-DAC '98, 1998

1997
Time-constrained code compaction for DSPs.
IEEE Trans. VLSI Syst., 1997

Guest Editor's Introduction: Design, Design Automation, and Test in Europe.
IEEE Design & Test of Computers, 1997

An Algorithm for Hardware/Software Partitioning Using Mixed Integer Linear Programming.
Design Autom. for Emb. Sys., 1997

A New Optimization Technique for Improving Resource Exploitation and Critical Path Minimization.
Proceedings of the 10th International Symposium on System Synthesis, 1997

Retargetable generation of code selectors from HDL processor models.
Proceedings of the European Design and Test Conference, 1997

Code Generation for Core Processors.
Proceedings of the 34st Conference on Design Automation, 1997

Built-in chaining: introducing complex components into architectural synthesis.
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

Processor-core based design and test.
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

1996
Hardware-Software Co-Design for Test: It's the Last Straw!
Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

Instruction-Set Modeling for ASIP Code Generation.
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

Algorithms for address assignment in DSP code generation.
Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

Instruction selection for embedded DSPs with complex instructions.
Proceedings of the conference on European design automation, 1996

Hardware/Software Partitioning using Integer Programming.
Proceedings of the 1996 European Design and Test Conference, 1996

A Technique for Avoiding Isomorphic Netlists in Architectural Synthesis.
Proceedings of the 1996 European Design and Test Conference, 1996

1995
A BDD-based frontend for retargetable compilers.
Proceedings of the 1995 European Design and Test Conference, 1995

Retargetable Self-Test Program Generation Using Constraint Logic Programming.
Proceedings of the 32st Conference on Design Automation, 1995

Using compilers for heterogeneous system design.
Proceedings of the IFIP WG10.3 working conference on Parallel architectures and compilation techniques, 1995

1994
ASICs vs ASIPs (panel).
Proceedings of the 7th International Symposium on High Level Synthesis, 1994

Retargetable assembly code generation by bootstrapping.
Proceedings of the 7th International Symposium on High Level Synthesis, 1994

Microcode Generation for Flexible Parallel Target Architectures.
Proceedings of the Parallel Architectures and Compilation Techniques, 1994

Instruction set extraction from programmable structures.
Proceedings of the Proceedings EURO-DAC'94, 1994

OSCAR: optimum simultaneous scheduling, allocation and resource binding based on integer programming.
Proceedings of the Proceedings EURO-DAC'94, 1994

Code generation for embedded processors: an introduction.
Proceedings of the Code Generation for Embedded Processors [Dagstuhl Workshop, Dagstuhl, Germany, August 31, 1994

1993
Tree-based mapping of algorithms to predefined structures.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

Synthese und Simulation von VLSI-Systemen - Algorithmen für den rechnerunterstützten Entwurf hochintegrierter Schaltungen.
Hanser-Studien-Bücher, Hanser, ISBN: 978-3-446-16146-7, 1993

1992
Synthese von Register-Transfer-Strukturen aus Verhaltensbeschriebungen.
Informatik Spektrum, 1992

Implementations of IF-statements in the TODOS microarchitecture synthesis system.
Proceedings of the Synthesis for Control Dominated Circuits, 1992

1990
Matching system and component behaviour in MIMOLA synthesis tools.
Proceedings of the European Design Automation Conference, 1990

Ein Software-System zur Synthese von Rechnerstrukturen und zur Erzeugung von Mikrocode.
PhD thesis, 1990

1989
Verification of Hardware Descriptions by Retargetable Code Generation.
Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

Integrated Scheduling and Binding: A Synthesis Approach for Design Space Exploration.
Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

1988
Ein retargierbarer Mikrocode-Compiler und seine Anwendung in Entwurfsverifikation und Architekturbewertung.
Proceedings of the GI, 1988

1986
A new synthesis for the MIMOLA software system.
Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, 1986

1984
A retargetable compiler for a high-level microprogramming language.
Proceedings of the 17th annual workshop on Microprogramming, 1984

The mimola design system: Tools for the design of digital processors.
Proceedings of the 21st Design Automation Conference, 1984

1982
The Integrated Design of Computer Systems with Mimola.
Proceedings of the GI - 12. Jahrestagung, Kaiserslautern, 5. -7. Oktober 1982, Proceedings, 1982

1981
A retargetable microcode generation system for a high-level microprogramming language.
Proceedings of the 14th annual workshop on Microprogramming, 1981

1980
The Design of a Subprocessor with Dynamic Microprogramming with MIMOLA.
Proceedings of the GI-NTG Fachtagung Struktur und Betrieb von Rechensystemen, 1980

1979
The MIMOLA design system: Detailed description of the software system.
Proceedings of the 16th Design Automation Conference, 1979


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