Chenxi Han

Orcid: 0000-0003-4053-5897

According to our database1, Chenxi Han authored at least 8 papers between 2022 and 2025.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2025
A Reference-Less CDR Using SAR-Based Frequency-Acquisition Technique Achieving 55ns Constant Band-Searching Time and up to 63.64Gb/s/µs Acquisition Speed.
Proceedings of the IEEE International Solid-State Circuits Conference, 2025

A 100Gb/s Transmitter with Digital Pre-Distortion and MUX-Merged Voltage-Mode Driver Achieving 3-Times INLPP Improvement in 28nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2025

2024
A 56 Gb/s DAC-DSP-based transmitter with adaptive retiming clock optimization using inverse-PR-based PD achieving 8-UI converge time in 28-nm CMOS.
Sci. China Inf. Sci., 2024

Structural Optimization of Lightweight Bipedal Robot via SERL.
Proceedings of the IEEE/RSJ International Conference on Intelligent Robots and Systems, 2024

2023
An All-Digital Background Calibration Technique for M-Channel Downsampling Time-Interleaved ADCs Based on Interpolation.
IEEE Trans. Circuits Syst. II Express Briefs, June, 2023

A digital calibration technique for <i>N</i>-channel time-interleaved ADC based on simulated annealing algorithm.
Microelectron. J., March, 2023

An Energy-Efficient SAR ADC With a Coarse-Fine Bypass Window Technique.
IEEE Trans. Circuits Syst. I Regul. Pap., January, 2023

2022
An efficient EEGNet processor design for portable EEG-Based BCIs.
Microelectron. J., 2022


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