Chi-Chun Yang

According to our database, Chi-Chun Yang authored at least 5 papers between 2013 and 2025.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of five.

2025

DFT Techniques For Efficient 3D IC Interconnect Test For Chiplet and Multi-Die Package.

Anshuman Chandra, Chi-Chun Yang, Quoc Phan, Martin Keim

Proceedings of the IEEE European Test Symposium, 2025

2015

A hybrid built-in self-test scheme for DRAMs.

Chi-Chun Yang, Jin-Fu Li, Yun-Chao Yu, Kuan-Te Wu, Chih-Yen Lo, Chao-Hsun Chen, Jenn-Shiang Lai, Ding-Ming Kwai, Yung-Fa Chou

Proceedings of the VLSI Design, Automation and Test, 2015

2014

BIST-Assisted Tuning Scheme for Minimizing IO-Channel Power of TSV-Based 3D DRAMs.

Yun-Chao You, Chi-Chun Yang, Jin-Fu Li, Chih-Yen Lo, Chao-Hsun Chen, Jenn-Shiang Lai, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu

Proceedings of the 23rd IEEE Asian Test Symposium, 2014

Intra-channel Reconfigurable Interface for TSV and Micro Bump Fault Tolerance in 3-D RAMs.

Kuan-Te Wu, Jin-Fu Li, Yun-Chao Yu, Chih-Sheng Hou, Chi-Chun Yang, Ding-Ming Kwai, Yung-Fa Chou, Chih-Yen Lo

Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2013

A TSV Repair Scheme Using Enhanced Test Access Architecture for 3-D ICs.

Chi-Chun Yang, Che-Wei Chou, Jin-Fu Li

Proceedings of the 22nd Asian Test Symposium, 2013