Chia-En Huang

According to our database, Chia-En Huang authored at least 4 papers between 2011 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2021

A 16Kb Antifuse One-Time-Programmable Memory in 5nm High-K Metal-Gate Fin-FET CMOS Featuring Bootstrap High Voltage Scheme, Read Endpoint Detection and Pseudo-Differential Sensing.

Shaun Chou, Gu-Huan Li, Shawn Chen, Jun-Hao Chang, Wan-Hsueh Cheng, Shao-Ding Wu, Philex Fan, Chia-En Huang, Yu-Der Chih, Yih Wang, Jonathan Chang

Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

2014

Control of a pneumatic power active lower-limb orthosis with filter-based iterative learning control.

Chia-En Huang, Jian-Shiang Chen

Int. J. Syst. Sci., 2014

2012

A 28nm high-k metal-gate SRAM with Asynchronous Cross-Couple Read Assist (AC²RA) circuitry achieving 3x reduction on speed variation for single ended arrays.

Robin Lee, Jung-Ping Yang, Chia-En Huang, Chih-Chieh Chiu, Wei-Shuo Kao, Hong-Chen Cheng, Hong-Jen Liao, Jonathan Chang

Proceedings of the Symposium on VLSI Circuits, 2012

2011

An offset-tolerant current-sampling-based sense amplifier for Sub-100nA-cell-current nonvolatile memory.

Meng-Fan Chang, Shin-Jang Shen, Chia-Chi Liu, Che-Wei Wu, Yu-Fan Lin, Shang-Chi Wu, Chia-En Huang, Han-Chao Lai, Ya-Chin King, Chorng-Jung Lin, Hung-Jen Liao, Yu-Der Chih, Hiroyuki Yamauchi

Proceedings of the IEEE International Solid-State Circuits Conference, 2011