Ya-Chin King

Orcid: 0000-0003-4065-0350

According to our database1, Ya-Chin King authored at least 26 papers between 2004 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2023
High Density Embedded 3D Stackable Via RRAM in Advanced MCU Applications.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

2020
Embedded 1-Mb ReRAM-Based Computing-in- Memory Macro With Multibit Input and Weight for CNN-Based AI Edge Processors.
IEEE J. Solid State Circuits, 2020

2019
Dynamic pH Sensor with Embedded Calibration Scheme by Advanced CMOS FinFET Technology.
Sensors, 2019

Self-Convergent Trimming SRAM True Random Number Generation With In-Cell Storage.
IEEE J. Solid State Circuits, 2019

A ReRAM Macro Using Dynamic Trip-Point-Mismatch Sampling Current-Mode Sense Amplifier and Low-DC Voltage-Mode Write-Termination Scheme Against Resistance and Write-Delay Variation.
IEEE J. Solid State Circuits, 2019

FinFET CMOS logic gates with non-volatile states for reconfigurable computing systems.
Integr., 2019

A 1Mb Multibit ReRAM Computing-In-Memory Macro with 14.6ns Parallel MAC Computing Time for CNN Based AI Edge Processors.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2018
A 65nm 1Mb nonvolatile computing-in-memory ReRAM macro with sub-16ns multiply-and-accumulate for binary DNN AI edge processors.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2017
A 65-nm ReRAM-Enabled Nonvolatile Processor With Time-Space Domain Adaption and Self-Write-Termination Achieving > 4× Faster Clock Frequency and > 6× Higher Restore Speed.
IEEE J. Solid State Circuits, 2017

A ReRAM-Based Nonvolatile Flip-Flop With Self-Write-Termination Scheme for Frequent-OFF Fast-Wake-Up Nonvolatile Processors.
IEEE J. Solid State Circuits, 2017

2016
4.7 A 65nm ReRAM-enabled nonvolatile processor with 6× reduction in restore time and 4× higher clock frequency using adaptive data retention and self-write-termination nonvolatile logic.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

7.4 A 256b-wordlength ReRAM-based TCAM with 1ns search-time and 14× improvement in wordlength-energyefficiency-density product using 2.5T1R cell.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015
Low VDDmin Swing-Sample-and-Couple Sense Amplifier and Energy-Efficient Self-Boost-Write-Termination Scheme for Embedded ReRAM Macros Against Resistance and Switch-Time Variations.
IEEE J. Solid State Circuits, 2015

Challenges and Circuit Techniques for Energy-Efficient On-Chip Nonvolatile Memory Using Memristive Devices.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2015

2014
Area-Efficient Embedded Resistive RAM (ReRAM) Macros Using Logic-Process Vertical-Parasitic-BJT (VPBJT) Switches and Read-Disturb-Free Temperature-Aware Current-Mode Read Scheme.
IEEE J. Solid State Circuits, 2014

19.4 embedded 1Mb ReRAM in 28nm CMOS with 0.27-to-1V read using swing-sample-and-couple sense amplifier and self-boost-write-termination scheme.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

A low-power subthreshold-to-superthreshold level-shifter for sub-0.5V embedded resistive RAM (ReRAM) macro in ultra low-voltage chips.
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

2013
A Low-Voltage Bulk-Drain-Driven Read Scheme for Sub-0.5 V 4 Mb 65 nm Logic-Process Compatible Embedded Resistive RAM (ReRAM) Macro.
IEEE J. Solid State Circuits, 2013

An Offset-Tolerant Fast-Random-Read Current-Sampling-Based Sense Amplifier for Small-Cell-Current Nonvolatile Memory.
IEEE J. Solid State Circuits, 2013

2012
A 0.5V 4Mb logic-process compatible embedded resistive RAM (ReRAM) in 65nm CMOS using low-voltage current-mode sensing scheme with 45ns random read time.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2011
An offset-tolerant current-sampling-based sense amplifier for Sub-100nA-cell-current nonvolatile memory.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2005
Low-cost logarithmic CMOS image sensing by nonlinear analog-to-digital conversion.
IEEE Trans. Consumer Electron., 2005

Gate stress effect on low temperature data retention characteristics of split-gate flash memories.
Microelectron. Reliab., 2005

A novel single poly-silicon EEPROM using trench floating gate.
Proceedings of the 13th IEEE International Workshop on Memory Technology, 2005

Novel self-convergent scheme logic-process-based multilevel/analog EEPROM memory.
Proceedings of the 13th IEEE International Workshop on Memory Technology, 2005

2004
Reliability Evaluation and Redesign of LNA.
Microelectron. Reliab., 2004


  Loading...