Ying Cao

Affiliations:
  • Xilinx, Inc., San Jose, CA, USA


According to our database1, Ying Cao authored at least 6 papers between 2018 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
A O.96pJ/b 7 × 50Gb/s-per-Fiber WDM Receiver with Stacked 7nm CMOS and 45nm Silicon Photonic Dies.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

2022
A 1.24-pJ/b 112-Gb/s (870 Gb/s/Mm) Transceiver for In-Package Links in 7-nm FinFET.
IEEE J. Solid State Circuits, 2022

2021
A 112-Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR ADC and Inverter-Based RX Analog Front-End in 7-nm FinFET.
IEEE J. Solid State Circuits, 2021

A 1.24pJ/b 112Gb/s (870Gbps/mm) Transceiver for In-package Links in 7nm FinFET.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

2020
6.1 A 112Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR-ADC and Inverter-Based RX Analog Front-End in 7nm FinFET.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2018
A 7.4-to-14GHz PLL with 54fsrms jitter in 16nm FinFET for integrated RF-data-converter SoCs.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018


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