Davide Rossetti
Orcid: 0000-0002-5113-1102
According to our database1,
Davide Rossetti
authored at least 30 papers
between 1997 and 2022.
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Bibliography
2022
Architectural improvements and technological enhancements for the APEnet+ interconnect system.
CoRR, 2022
2021
Concurr. Comput. Pract. Exp., 2021
2018
GPUDirect Async: Exploring GPU synchronous communication techniques for InfiniBand clusters.
J. Parallel Distributed Comput., 2018
2017
MPI-GDS: High Performance MPI Designs with GPUDirect-aSync for CPU-GPU Control Flow Decoupling.
Proceedings of the 46th International Conference on Parallel Processing, 2017
GPU-Centric Communication on NVIDIA GPU Clusters with InfiniBand: A Case Study with OpenSHMEM.
Proceedings of the 24th IEEE International Conference on High Performance Computing, 2017
Proceedings of the 17th IEEE/ACM International Symposium on Cluster, 2017
2016
Dynamic many-process applications on many-tile embedded systems and HPC clusters: The EURETILE programming environment and execution platforms.
J. Syst. Archit., 2016
2015
ASIP acceleration for virtual-to-physical address translation on RDMA-enabled FPGA-based network interfaces.
Future Gener. Comput. Syst., 2015
A hierarchical watchdog mechanism for systemic fault awareness on distributed systems.
Future Gener. Comput. Syst., 2015
Proceedings of the OpenSHMEM and Related Technologies. Experiences, Implementations, and Technologies, 2015
Proceedings of the 23rd IEEE Annual Symposium on High-Performance Interconnects, 2015
2014
NaNet: a Low-Latency, Real-Time, Multi-Standard Network Interface Card with GPUDirect Features.
CoRR, 2014
Proceedings of the 33rd IEEE International Symposium on Reliable Distributed Systems, 2014
Designing efficient small message transfer mechanism for inter-node MPI communication on InfiniBand GPU clusters.
Proceedings of the 21st International Conference on High Performance Computing, 2014
2013
J. Parallel Distributed Comput., 2013
NaNet: a flexible and configurable low-latency NIC for real-time trigger systems based on GPUs.
CoRR, 2013
A heterogeneous many-core platform for experiments on scalable custom interconnects and management of fault and critical events, applied to many-process applications: Vol. II, 2012 technical report.
CoRR, 2013
Architectural improvements and 28 nm FPGA implementation of the APEnet+ 3D Torus network for hybrid HPC systems.
CoRR, 2013
'Mutual Watch-dog Networking': Distributed Awareness of Faults and Critical Events in Petascale/Exascale systems.
CoRR, 2013
Design and implementation of a modular, low latency, fault-aware, FPGA-based network interface.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013
Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013
Virtual-to-Physical address translation for an FPGA-based interconnect with host and GPU remote DMA capabilities.
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013
2012
The Distributed Network Processor: a novel off-chip and on-chip interconnection network architecture
CoRR, 2012
Proceedings of the 2012 SC Companion: High Performance Computing, 2012
2011
APEnet+: high bandwidth 3D torus direct network for petaflops scale commodity clusters
CoRR, 2011
2010
APEnet+: a 3D toroidal network enabling Petaflops scale Lattice QCD simulations on commodity clusters
CoRR, 2010
2009
Synthesis of Communication Mechanisms for Multi-tile Systems Based on Heterogeneous Multi-processor System-On-Chips.
Proceedings of the Twentienth IEEE/IFIP International Symposium on Rapid System Prototyping, 2009
2006
2004
Proceedings of the 2004 IEEE International Conference on Cluster Computing (CLUSTER 2004), 2004
1997
Proceedings of the High-Performance Computing and Networking, 1997