David E. Lackey

According to our database1, David E. Lackey authored at least 10 papers between 1996 and 2010.

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Bibliography

2010
Low cost at-speed testing using On-Product Clock Generation compatible with test compression.
Proceedings of the 2011 IEEE International Test Conference, 2010

2007
An Integrated Framework for At-Speed and ATE-Driven Delay Test of Contract-Manufactured ASICs.
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Variation-aware performance verification using at-speed structural test and statistical timing.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

2006
Efficient Latch and Clock Structures for System-on-Chip Test Flexibility.
Proceedings of the 2006 IEEE International Test Conference, 2006

2003
Designing mega-ASICs in nanogate technologies.
Proceedings of the 40th Design Automation Conference, 2003

IBM's 50 Million gate ASICs.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002
The IBM ASIC/SoC methodology - A recipe for first-time success.
IBM J. Res. Dev., 2002

Managing power and performance for System-on-Chip designs using Voltage Islands.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

2000
Applying placement-based synthesis for on-time system-on-a-chip design.
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000

1996
Design methodology for IBM ASIC products.
IBM J. Res. Dev., 1996


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