Chandu Visweswariah

Affiliations:
  • Thomas J. Watson Research Center, Yorktown Heights, USA


According to our database1, Chandu Visweswariah authored at least 36 papers between 1992 and 2016.

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Bibliography

2016
Managing uncertainty in electricity generation and demand forecasting.
IBM J. Res. Dev., 2016

2013
Order statistics for correlated random variables and its application to at-speed testing.
ACM Trans. Design Autom. Electr. Syst., 2013

Speeding up computation of the max/min of a set of gaussians for statistical timing analysis and optimization.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012
A Novel Method for Reducing Metal Variation With Statistical Static Timing Analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

A dynamic method for efficient random mismatch characterization of standard cells.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Timing analysis with nonseparable statistical and deterministic variations.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Reversible statistical <i>max/min</i> operation: concept and applications to timing.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2010
Statistical Path Selection for At-Speed Test.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Transistor sizing of custom high-performance digital circuits with parametric yield considerations.
Proceedings of the 47th Design Automation Conference, 2010

2009
Optimal Test Margin Computation for At-Speed Structural Test.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Feasible Aggressor-Set Identification Under Constraints for Maximum Coupling Noise.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Statistical Power Analysis for High-Performance Processors.
J. Low Power Electron., 2009

Special Session 8: New Topics: At-Speed Testing in the Face of Process Variations.
Proceedings of the 27th IEEE VLSI Test Symposium, 2009

A New Methodology for Power-Aware Transistor Sizing: Free Power Recovery (FPR).
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009

Voltage binning under process variation.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

Pre-ATPG path selection for near optimal post-ATPG process space coverage.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

Statistical ordering of correlated timing quantities and its application for path ranking.
Proceedings of the 46th Design Automation Conference, 2009

Statistical multilayer process space coverage for at-speed test.
Proceedings of the 46th Design Automation Conference, 2009

A moment-based effective characterization waveform for static timing analysis.
Proceedings of the 46th Design Automation Conference, 2009

2008
Statistical Modeling and Analysis of Static Leakage and Dynamic Switching Power.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008

Plenary Speech 2P2: Statistical Techniques to Achieve Robustness and Quality.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Optimal Margin Computation for At-Speed Test.
Proceedings of the Design, Automation and Test in Europe, 2008

Incremental Criticality and Yield Gradients.
Proceedings of the Design, Automation and Test in Europe, 2008

Static timing: Back to our roots.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
Fear, uncertainty and statistics.
Proceedings of the 2007 International Symposium on Physical Design, 2007

Compact modeling of variational waveforms.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Variation-aware performance verification using at-speed structural test and statistical timing.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

2006
Statistical analysis and optimization in the presence of gate and interconnect delay variations.
Proceedings of the Eigth International Workshop on System-Level Interconnect Prediction (SLIP 2006), 2006

Criticality computation in parameterized statistical timing.
Proceedings of the 43rd Design Automation Conference, 2006

2005
Gate sizing using incremental parameterized statistical timing analysis.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Parameterized block-based statistical timing analysis with non-gaussian parameters, nonlinear delay functions.
Proceedings of the 42nd Design Automation Conference, 2005

2004
Statistical analysis and design: from picoseconds to probabilities.
Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, 2004

2003
Time Budgeting in a Wireplanning Context.
Proceedings of the 2003 Design, 2003

Death, taxes and failing chips.
Proceedings of the 40th Design Automation Conference, 2003

1999
Two-Step Algorithms for Nonlinear Optimization with Structured Applications.
SIAM J. Optim., 1999

1992
Stepsize Control in Piecewise Approximate Circuit Simulation.
Proceedings of the Fifth International Conference on VLSI Design, 1992


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