Jiaxin Liu

According to our database, Jiaxin Liu authored at least 40 papers between 2018 and 2026.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2026

A 30kHz-BW 100.6dB-SNDR ΔΣ Modulator with Swapped Sampling-Feedback Operation and Optimized kT/C Noise Cancellation.

Xuanhao Zhang, Han Zhao, Congyu Jin, Hongshuai Zhang, Zheng Wang, Zhong Zhang, Ning Ning, Zhenbing Li, Xiangyu Mao, Shiheng Yang, Jiaxin Liu

Proceedings of the IEEE Custom Integrated Circuits Conference, 2026

A 3.6mW 5MS/s 100dB-SNDR 2-Step SAR ADC with Continuous-Time Second-Stage and Tracking Averaging.

Congyu Jin, Zhaoyang Shen, Xingshuai Zou, Xuanhao Zhang, Han Zhao, Zhong Zhang, Ning Ning, Hongshuai Zhang, Zheng Wang, Zhenbing Li, Shiheng Yang, Xiangyu Mao, Jiaxin Liu

Proceedings of the IEEE Custom Integrated Circuits Conference, 2026

2025

A 5-MS/s 93.4-dB-DR Three-Step Incremental Zoom ADC With Single Sampling.

Xuanhao Zhang, Jialin Hu, Xingshuai Zou, Shiheng Yang, Jiaxin Liu

IEEE Trans. Circuits Syst. I Regul. Pap., October, 2025

Analyses Concerning the Phase Noise and Nonlinear Behavior of the Charge-Sharing Integrator-Based Hybrid PLL.

Jingrun Song, Xinyu Yang, Jiaxu Liu, Yueduo Liu, Zihao Zhu, Zhengxuan Han, Zehao Zhang, Jiaxin Liu, Hongshuai Zhang, Jun Yin, Pui-In Mak, Shiheng Yang

IEEE Trans. Circuits Syst. I Regul. Pap., July, 2025

18.1 A Fully Dynamic Noise-Shaping SAR ADC Achieving 120dB SNDR and 189dB FoMs in 1kHz BW.

Han Zhao, Xuanhao Zhang, Qijin Deng, Jialin Hu, Zhenbing Li, Shiheng Yang, Jiaxin Liu

Proceedings of the IEEE International Solid-State Circuits Conference, 2025

A 0.4μW/MHz Reference-Replication-Based RC Oscillator with Path-Delay and Comparator-Offset Cancellation Achieving 9.83ppm/°C from -40 to 125°C.

Yueduo Liu, Zihao Zhu, Xinyu Yang, Rongxin Bao, Zehao Zhang, Hongshuai Zhang, Jiaxin Liu, Zheng Wang, Mingkang Zhang, Na Yan, Jun Yin, Pui-In Mak, Shiheng Yang

Proceedings of the IEEE International Solid-State Circuits Conference, 2025

2024

An Energy-Efficient Computing-in-Memory NN Processor With Set-Associate Blockwise Sparsity and Ping-Pong Weight Update.

Jinshan Yue, Yongpan Liu, Xiaoyu Feng, Yifan He, Jingyu Wang, Zhe Yuan, Mingtao Zhan, Jiaxin Liu, Jian-Wei Su, Yen-Lin Chung, Ping-Chun Wu, Li-Yang Hong, Meng-Fan Chang, Nan Sun, Chunmeng Dou, Xueqing Li, Ming Liu, Huazhong Yang

IEEE J. Solid State Circuits, May, 2024

Mitigating Sampling Noise for Energy-Efficient ADCs: A Tutorial Brief.

Chang Liu, Jiaxin Liu, Nan Sun

IEEE Trans. Circuits Syst. II Express Briefs, March, 2024

A Noise Shaping SAR ADC with kT/C Noise Cancellation and Mismatch Error Shaping.

Tiange Yi, Zhenbing Li, Bing Du, Shiheng Yang, Jiaxin Liu

Proceedings of the IEEE International Conference on Integrated Circuits, 2024

2023

A Bandwidth-Adaptive Pipelined SAR ADC With Three-Stage Cascoded Floating Inverter Amplifier.

Xiyuan Tang, Xiangxing Yang, Jiaxin Liu, Zongnan Wang, Wei Shi, David Z. Pan, Nan Sun

IEEE J. Solid State Circuits, September, 2023

SAMBA: Single-ADC Multi-Bit Accumulation Compute-in-Memory Using Nonlinearity- Compensated Fully Parallel Analog Adder Tree.

Yiming Chen, Guodong Yin, Mufeng Zhou, Wenjun Tang, Zekun Yang, Mingyen Lee, Xirui Du, Jinshan Yue, Jiaxin Liu, Huazhong Yang, Yongpan Liu, Xueqing Li

IEEE Trans. Circuits Syst. I Regul. Pap., July, 2023

On the DC-Settling Process of the Pierce Crystal Oscillator in Start-Up.

Zehao Zhang, Shiheng Yang, Yueduo Liu, Zihao Zhu, Jiahui Lin, Rongxin Bao, Tailong Xu, Zhizhan Yang, Mingkang Zhang, Jiaxin Liu, Xiong Zhou, Jun Yin, Pui-In Mak, Qiang Li

IEEE Trans. Circuits Syst. II Express Briefs, 2023

2022

Low-Power SAR ADC Design: Overview and Survey of State-of-the-Art Techniques.

Xiyuan Tang, Jiaxin Liu, Yi Shen, Shaolan Li, Linxiao Shen, Arindam Sanyal, Kareem Ragab, Nan Sun

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

A 65nm 8b-Activation 8b-Weight SRAM-Based Charge-Domain Computing-in-Memory Macro Using A Fully-Parallel Analog Adder Network and A Single-ADC Interface.

Guodong Yin, Mufeng Zhou, Yiming Chen, Wenjun Tang, Zekun Yang, Mingyen Lee, Xirui Du, Jinshan Yue, Jiaxin Liu, Huazhong Yang, Yongpan Liu, Xueqing Li

CoRR, 2022

A 4.2-to-5.6 GHz Transformer-Based PMOS-only Stacked-gm VCO in 28-nm CMOS.

Mingkang Zhang, Zihao Zhu, Yueduo Liu, Zehao Zhang, Rongxin Bao, Jiahui Lin, Haovu Zhuang, Jiaxin Liu, Xiong Zhou, Shiheng Yang, Qiang Li

Proceedings of the 2022 IEEE International Conference on Integrated Circuits, 2022

2021

A Fully Dynamic Low-Power Wideband Time-Interleaved Noise-Shaping SAR ADC.

Haoyu Zhuang, Jiaxin Liu, He Tang, Xizhu Peng, Nan Sun

IEEE J. Solid State Circuits, 2021

A 90-dB-SNDR Calibration-Free Fully Passive Noise-Shaping SAR ADC With 4× Passive Gain and Second-Order DAC Mismatch Error Shaping.

Jiaxin Liu, Xing Wang, Zijie Gao, Mingtao Zhan, Xiyuan Tang, Chen-Kai Hsu, Nan Sun

IEEE J. Solid State Circuits, 2021

A 77.1-dB-SNDR 6.25-MHz-BW Pipeline SAR ADC With Enhanced Interstage Gain Error Shaping and Quantization Noise Shaping.

Chen-Kai Hsu, Xiyuan Tang, Jiaxin Liu, Rui Xu, Wenda Zhao, Abhishek Mukherjee, Timothy R. Andeen, Nan Sun

IEEE J. Solid State Circuits, 2021

A 2.75-to-75.9TOPS/W Computing-in-Memory NN Processor Supporting Set-Associate Block-Wise Zero Skipping and Ping-Pong CIM with Simultaneous Computation and Weight Updating.

Jinshan Yue, Xiaoyu Feng, Yifan He, Yuxuan Huang, Yipeng Wang, Zhe Yuan, Mingtao Zhan, Jiaxin Liu, Jian-Wei Su, Yen-Lin Chung, Ping-Chun Wu, Li-Yang Hung, Meng-Fan Chang, Nan Sun, Xueqing Li, Huazhong Yang, Yongpan Liu

Proceedings of the IEEE International Solid-State Circuits Conference, 2021

A 0.4-to-40MS/s 75.7dB-SNDR Fully Dynamic Event-Driven Pipelined ADC with 3-Stage Cascoded Floating Inverter Amplifier.

Xiyuan Tang, Xiangxing Yang, Jiaxin Liu, Wei Shi, David Z. Pan, Nan Sun

Proceedings of the IEEE International Solid-State Circuits Conference, 2021

10.4 A 3.7mW 12.5MHz 81dB-SNDR 4th-Order CTDSM with Single-OTA and 2nd-Order NS-SAR.

Wei Shi, Jiaxin Liu, Abhishek Mukherjee, Xiangxing Yang, Xiyuan Tang, Linxiao Shen, Wenda Zhao, Nan Sun

Proceedings of the IEEE International Solid-State Circuits Conference, 2021

27.1 A 250kHz-BW 93dB-SNDR 4^th-Order Noise-Shaping SAR Using Capacitor Stacking and Dynamic Buffering.

Jiaxin Liu, Dengquan Li, Yi Zhong, Xiyuan Tang, Nan Sun

Proceedings of the IEEE International Solid-State Circuits Conference, 2021

A Low-Power RC Oscillator with Offset and Path Delay Cancellation.

Yueduo Liu, Zihao Zhu, Rongxin Bao, Shiheng Yang, Jiaxin Liu, Xiong Zhou, Qiang Li

Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021

An 81.5dB-DR 1.25MHz-BW VCO-Based CT ΔΣ ADC with Double-PFD Quantizer.

Yi Zhong, Xiyuan Tang, Jiaxin Liu, Wenda Zhao, Shaolan Li, Nan Sun

Proceedings of the IEEE Custom Integrated Circuits Conference, 2021

A 640×512 30μm Pixel Pitch 1.8mK-NETD 90.1dB-SNR Digital Read-out Integrated Circuit with Fully On-chip Image Algorithm Pixel-Level Calibration.

Yan Zeng, Shiheng Yang, Yueduo Liu, Zehao Li, Wengang Huang, Xiaozong Huang, Xiong Zhou, Jiaxin Liu, Qiang Li

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021

A Low Power Sample-and-Hold Circuit with Improved Dynamic Bias for Pipelined ADC.

Xiaodan Zhou, Zehao Li, Yujie Wang, Xiong Zhou, Shiheng Yang, Jiaxin Liu, Qiang Li

Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2021

2020

A 13.5-ENOB, 107-μW Noise-Shaping SAR ADC With PVT-Robust Closed-Loop Dynamic Amplifier.

Xiyuan Tang, Xiangxing Yang, Wenda Zhao, Chen-Kai Hsu, Jiaxin Liu, Linxiao Shen, Abhishek Mukherjee, Wei Shi, Shaolan Li, David Z. Pan, Nan Sun

IEEE J. Solid State Circuits, 2020

An Energy-Efficient Time-Domain Incremental Zoom Capacitance-to-Digital Converter.

Xiyuan Tang, Shaolan Li, Xiangxing Yang, Linxiao Shen, Wenda Zhao, Randall P. Williams, Jiaxin Liu, Zhichao Tan, Neal A. Hall, David Z. Pan, Nan Sun

IEEE J. Solid State Circuits, 2020

A 13-bit 0.005-mm² 40-MS/s SAR ADC With kT/C Noise Cancellation.

Jiaxin Liu, Xiyuan Tang, Wenda Zhao, Linxiao Shen, Nan Sun

IEEE J. Solid State Circuits, 2020

A 7-bit 900-MS/s 2-Then-3-bit/cycle SAR ADC With Background Offset Calibration.

Dengquan Li, Zhangming Zhu, Jiaxin Liu, Haoyu Zhuang, Yintang Yang, Nan Sun

IEEE J. Solid State Circuits, 2020

9.5 A 13.5b-ENOB Second-Order Noise-Shaping SAR with PVT-Robust Closed-Loop Dynamic Amplifier.

Xiyuan Tang, Xiangxing Yang, Wenda Zhao, Chen-Kai Hsu, Jiaxin Liu, Linxiao Shen, Abhishek Mukherjee, Wei Shi, David Z. Pan, Nan Sun

Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

9.3 A 40kHz-BW 90dB-SNDR Noise-Shaping SAR with 4× Passive Gain and 2^nd-Order Mismatch Error Shaping.

Jiaxin Liu, Xing Wang, Zijie Gao, Mingtao Zhan, Xiyuan Tang, Nan Sun

Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

16.5 A 13b 0.005mm² 40MS/s SAR ADC with kT/C Noise Cancellation.

Jiaxin Liu, Xiyuan Tang, Wenda Zhao, Linxiao Shen, Nan Sun

Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

A Fully-Dynamic Time-Interleaved Noise-Shaping SAR ADC Based on CIFF Architecture.

Haoyu Zhuang, Jiaxin Liu, Nan Sun

Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020

2019

Error-Feedback Mismatch Error Shaping for High-Resolution Data Converters.

Jiaxin Liu, Chen-Kai Hsu, Xiyuan Tang, Shaolan Li, Guangjun Wen, Nan Sun

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A Second-Order Noise-Shaping SAR ADC With Passive Integrator and Tri-Level Voting.

Haoyu Zhuang, Wenjuan Guo, Jiaxin Liu, He Tang, Zhangming Zhu, Long Chen, Nan Sun

IEEE J. Solid State Circuits, 2019

A 0.029-mm² 17-fJ/Conversion-Step Third-Order CT ΔΣ ADC With a Single OTA and Second-Order Noise-Shaping SAR Quantizer.

Jiaxin Liu, Shaolan Li, Wenjuan Guo, Guangjun Wen, Nan Sun

IEEE J. Solid State Circuits, 2019

A 16fJ/Conversion-Step Time-Domain Two-Step Capacitance-to-Digital Converter.

Xiyuan Tang, Shaolan Li, Linxiao Shen, Wenda Zhao, Xiangxing Yang, Randy Williams, Jiaxin Liu, Zhichao Tan, Neal A. Hall, Nan Sun

Proceedings of the IEEE International Solid- State Circuits Conference, 2019

A 7b 2.6mW 900MS/s Nonbinary 2-then-3b/cycle SAR ADC with Background Offset Calibration.

Dengquan Li, Jiaxin Liu, Haoyu Zhuang, Zhangming Zhu, Yintang Yang, Nan Sun

Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

2018

A 0.029MM2 17-FJ/Conv.-Step CT $\Delta\Sigma$ ADC with 2^nd-Order Noise-Shaping SAR Quantizer.

Jiaxin Liu, Shaolan Li, Wenjuan Guo, Guangjun Wen, Nan Sun

Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018