Depeng Sun
Orcid: 0009-0002-2646-0235
According to our database1,
Depeng Sun
authored at least 12 papers
between 2020 and 2025.
Collaborative distances:
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Bibliography
2025
A 7.4-9.2-GHz Fractional-N Differential Sampling PLL Based on Phase-Domain and Voltage-Domain Hybrid Calibration.
IEEE Trans. Very Large Scale Integr. Syst., May, 2025
Design and analysis of an ultra-wideband quad-mode quad-core oscillator with mode ambiguity elimination.
Microelectron. J., 2025
A 1-V 3.9-5.2-GHz reference-sampling PLL with 168-fsrms integrated jitter and -76-dBc reference spur.
Microelectron. J., 2025
19.11 A 13GHz Charge-Pump PLL Achieving 15.8fs<sub>rms</sub> Integrated Jitter and -98.5dBc Reference Spur.
Proceedings of the IEEE International Solid-State Circuits Conference, 2025
2024
A 3.96-4.84-GHz Dual-Path Charge Pump PLL Achieving 89.7-fs<sub>rms</sub> Integrated Jitter and -250.8-dB FOM<sub>PLL</sub>.
IEEE Trans. Circuits Syst. II Express Briefs, April, 2024
A 39 GHz Doherty-Like Power Amplifier With 22dBm Output Power and 21% Power-Added Efficiency at 6dB Power Back-Off.
IEEE J. Emerg. Sel. Topics Circuits Syst., March, 2024
Microelectron. J., February, 2024
A low-noise, 0.05-17.8-GHz fractional-N phase-locked loop with two parallel synchronized dual-core voltage-controlled oscillators.
Microelectron. J., 2024
A 30.5-to-31 GHz Sampling PLL With Double-Edge Sampling PD and Implict Common-Mode VCO Scoring 39.69-fs RMS Jitter and -253.6-dB FoM in a 0.047mm<sup>2</sup> Area.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
A 0.0006-mm<sup>2</sup> 0.13-pJ/bit 9-21-Gb/s Sampling CDR with Inverter-Based Frequency Multiplier and Embedded 1: 3 DEMUX in 65-nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2024
2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
2020