Divya Pathak

Orcid: 0009-0004-6261-980X

According to our database1, Divya Pathak authored at least 25 papers between 2014 and 2025.

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Bibliography

2025
ITBench: Evaluating AI Agents across Diverse Real-World IT Automation Tasks.
CoRR, February, 2025

Metric Criticality Identification for Cloud Microservices.
CoRR, January, 2025

Demonstration of Dynamic Logging Framework for Cloud Native Environments.
Proceedings of the 17th International Conference on COMmunication Systems and NETworks, 2025

2024
Anomaly Detection in In-Network Fast ReRoute Systems.
Proceedings of the IFIP Networking Conference, 2024

Securing In-Network Fast Control Loop Systems from Adversarial Attacks.
Proceedings of the 16th International Conference on COMmunication Systems & NETworkS, 2024

Self Adjusting Log Observability for Cloud Native Applications.
Proceedings of the 17th IEEE International Conference on Cloud Computing, 2024

2023
Accelerating PUF-based Authentication Protocols Using Programmable Switch.
Proceedings of the NOMS 2023, 2023

Preference for Happy Faces in Emotion-based Attentional Priority in Visual Short Term Memory.
Proceedings of the 45th Annual Meeting of the Cognitive Science Society, 2023

2022
Accelerating PUF-based UAV Authentication Protocols Using Programmable Switch.
Proceedings of the 14th International Conference on COMmunication Systems & NETworkS, 2022

2021
A Novel Methodology For Crowdsourcing AI Models in an Enterprise.
CoRR, 2021

2020
WNTRAC: Artificial Intelligence Assisted Tracking of Non-pharmaceutical Interventions Implemented Worldwide for COVID-19.
CoRR, 2020

A Canonical Architecture For Predictive Analytics on Longitudinal Patient Records.
CoRR, 2020

Timely and Efficient AI Insights on EHR: System Design.
Proceedings of the AMIA 2020, 2020

2019
Applying Swarm Intelligence to Distributed On-Chip Power Management.
Proceedings of the 37th IEEE International Conference on Computer Design, 2019

2018
ElasticCore: A Dynamic Heterogeneous Platform With Joint Core and Voltage/Frequency Scaling.
IEEE Trans. Very Large Scale Integr. Syst., 2018

On-Chip Power Supply Noise Suppression Through Hyperabrupt Junction Varactors.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Power conversion efficiency-aware mapping of multithreaded applications on heterogeneous architectures: A comprehensive parameter tuning.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017
Smart Grid on Chip: Work Load-Balanced On-Chip Power Delivery.
IEEE Trans. Very Large Scale Integr. Syst., 2017

26.2 Power supply noise in a 22nm z13™ microprocessor.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

Work Load Scheduling For Multi Core Systems With Under-Provisioned Power Delivery.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

2016
Energy efficient on-chip power delivery with run-time voltage regulator clustering.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Load Balanced On-Chip Power Delivery for Average Current Demand.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

2015
Realizing complexity-effective on-chip power delivery for many-core platforms by exploiting optimized mapping.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

ElasticCore: enabling dynamic heterogeneity with joint core and voltage/frequency scaling.
Proceedings of the 52nd Annual Design Automation Conference, 2015

2014
Run-time voltage detection circuit for 3-D IC power delivery.
Proceedings of the 27th IEEE International System-on-Chip Conference, 2014


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