Ramon Bertran Monfort
According to our database1, Ramon Bertran Monfort authored at least 21 papers between 2010 and 2018.
Legend:Book In proceedings Article PhD thesis Other
Droop mitigation using critical-path sensors and an on-chip distributed power supply estimation engine in the z14™ enterprise processor.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
ChopStiX: Systematic Extraction of Code-Representative Microbenchmarks.
Proceedings of the 2018 IEEE International Symposium on Workload Characterization, 2018
Machine learning techniques for taming the complexity of modern hardware design.
IBM Journal of Research and Development, 2017
26.2 Power supply noise in a 22nm z13™ microprocessor.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
libPRISM: an intelligent adaptation of prefetch and SMT levels.
Proceedings of the International Conference on Supercomputing, 2017
Very Low Voltage (VLV) Design.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017
BRAVO: Balanced Reliability-Aware Voltage Optimization.
Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017
Robust power management in the IBM z13.
IBM Journal of Research and Development, 2015
Safe limits on voltage reduction efficiency in GPUs: a direct measurement approach.
Proceedings of the 48th International Symposium on Microarchitecture, 2015
Voltage Noise in Multi-Core Processors: Empirical Characterization and Optimization Opportunities.
Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014
Characterization of transient error tolerance for a class of mobile embedded applications.
Proceedings of the 2014 IEEE International Symposium on Workload Characterization, 2014
A Systematic Methodology to Generate Decomposable and Responsive Power Models for CMPs.
IEEE Trans. Computers, 2013
Application-level power and performance characterization and optimization on IBM Blue Gene/Q systems.
IBM Journal of Research and Development, 2013
Counter-Based Power Modeling Methods: Top-Down vs. Bottom-Up.
Comput. J., 2013
Energy accounting for shared virtualized environments under DVFS using PMC-based power models.
Future Generation Comp. Syst., 2012
POTRA: a framework for building power models for next generation multicore architectures.
Proceedings of the ACM SIGMETRICS/PERFORMANCE Joint International Conference on Measurement and Modeling of Computer Systems, 2012
Systematic Energy Characterization of CMP/SMT Processor Systems via Automated Micro-Benchmarks.
Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012
Local Memory Design Space Exploration for High-Performance Computing.
Comput. J., 2011
Design space exploration for aggressive core replication schemes in CMPs.
Proceedings of the 20th ACM International Symposium on High Performance Distributed Computing, 2011
Decomposable and responsive power models for multicore processors using performance counters.
Proceedings of the 24th International Conference on Supercomputing, 2010
Accurate energy accounting for shared virtualized environments using PMC-based power modeling techniques.
Proceedings of the 2010 11th IEEE/ACM International Conference on Grid Computing, 2010