Ho-Jin Park

According to our database1, Ho-Jin Park authored at least 36 papers between 2000 and 2017.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2017
Multiple-Loop Design Technique for High-Performance Low-Dropout Regulator.
IEEE J. Solid State Circuits, 2017

2016
8.3 A 200mA digital low-drop-out regulator with coarse-fine dual loop in mobile application processors.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

A high efficiency wide-load-range asynchronous boost converter with time-based dual-mode control for SSD applications.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

Multiple-loop design technique for high-performance low dropout regulator.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015
A Decision-Error-Tolerant 45 nm CMOS 7b 1 GS/s Nonbinary 2b/Cycle SAR ADC.
IEEE J. Solid State Circuits, 2015

26.4 A 21fJ/conv-step 9 ENOB 1.6GS/S 2× time-interleaved FATI SAR ADC with background offset and timing-skew calibration in 45nm CMOS.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

26.7 A 2.6b/cycle-architecture-based 10b 1 JGS/s 15.4mW 4×-time-interleaved SAR ADC with a multistep hardware-retirement technique.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014
A fully-differential capacitive touch controller with input common-mode feedback for symmetric display noise cancellation.
Proceedings of the Symposium on VLSI Circuits, 2014

2013
An 8.6 ENOB 900MS/s time-interleaved 2b/cycle SAR ADC with a 1b/cycle reconfiguration for resolution enhancement.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012
A 1.1 V 82.3dB audio ΔΣ ADC using asynchronous SAR type quantizer.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

A 7b 1GS/s 7.2mW nonbinary 2b/cycle SAR ADC with register-to-DAC direct control.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2010
A 10b 120MS/s 45nm CMOS ADC using A re-configurable three-stage switched op-amp.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009
An 11mW 100MHz 16X-OSR 64dB-SNDR hybrid CT/DT ΔΣ ADC with relaxed DEM timing.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

A 9.43-ENOB 160MS/s 1.2V 65nm CMOS ADC based on multi-stage amplifiers.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

Service Platform and Social Networking Service Based on Peer-to-Peer Networking.
Proceedings of the 6th IEEE Consumer Communications and Networking Conference, 2009

2008
Social Networking Service Based on Peer-to-Peer Network.
Proceedings of the 3rd International Conference on Systems and Networks Communications, 2008

A Peer-to-Peer Service Platform Architecture for Extended Home Services.
Proceedings of the Seventh International Conference on Networking (ICN 2008), 2008

A 16b 10MS/s digitally self-calibrated ADC with time constant control.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

A 101-dB SNR hybrid delta-sigma audio ADC using post integration time control.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007
A 14-b 30MS/s 0.75mm<sup>2</sup> Pipelined ADC with On-Chip Digital Self-Calibration.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

A Re-configurable 0.5V to 1.2V, 10MS/s to 100MS/s, Low-Power 10b 0.13um CMOS Pipeline ADC.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006
A Study on Architecture and Performance of Service Delivery Platform in Home Networks.
Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Networks, 2006

A Proposed Platform & Performance Estimation of Digital-Home Service Delivery/Management Systems.
Proceedings of the Third International Conference on Information Technology: New Generations (ITNG 2006), 2006

Developments and Performance Evaluation of Digital-Home Service Delivery & Management Systems.
Proceedings of the Fifth International Conference on Networking and the International Conference on Systems (ICN / ICONS / MCL 2006), 2006

A 4mW per-Channel 101dB-DR Stereo Audio DAC with Transformed Quantization Structure.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2005
Handover Mechanism for Differentiated QoS in High-Speed Portable Internet.
Proceedings of the Information Networking, 2005

2004
A 1.8V 8-bit 250Msample/s Nyquist-rate CMOS pipelined ADC.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A new enhanced management approach for heterogeneous service gateways.
Proceedings of the IASTED International Conference on Communications, Internet, and Information Technology, November 22, 2004

The proposal of the home device management mechanism on the heterogeneous residential gateway platform.
Proceedings of the IASTED International Conference on Communications, Internet, and Information Technology, November 22, 2004

A 2W, 92% efficiency and 0.01% THD+N class-D audio power amplifier for mobile applications, based on the novel SCOM architecture.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2003
A Study on B2C Based Electronic Commerce Payment System using the Telephone Number.
Proceedings of the Eighth IEEE Symposium on Computers and Communications (ISCC 2003), 30 June, 2003

2001
Open Software Architecture for Multiservice Switching System.
Proceedings of the Networking, 2001

2000
A 3.3 V 14-bit 10 MSPS calibration-free CMOS pipelined A/D converter.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

A 1 mW 10-bit 500KSPS SAR A/D converter.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

A DLL based 10-320 MHz clock synchronizer.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

A 1.4 V 10-bit 20 MSPS pipelined A/D converter.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000


  Loading...