Eduardo Chielle
Orcid: 0000-0002-1938-912X
  According to our database1,
  Eduardo Chielle
  authored at least 29 papers
  between 2011 and 2025.
  
  
Collaborative distances:
Collaborative distances:
Timeline
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Online presence:
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    on orcid.org
 
On csauthors.net:
Bibliography
  2025
PAPER: Privacy-Preserving ResNet Models using Low-Degree Polynomial Approximations and Structural Optimizations on Leveled FHE.
    
  
    CoRR, September, 2025
    
  
Recurrent Private Set Intersection for Unbalanced Databases with Cuckoo Hashing and Leveled FHE.
    
  
    Proceedings of the 32nd Annual Network and Distributed System Security Symposium, 2025
    
  
  2024
Coupling bit and modular arithmetic for efficient general-purpose fully homomorphic encryption.
    
  
    ACM Trans. Embed. Comput. Syst., July, 2024
    
  
Silicon-Proven ASIC Design for the Polynomial Operations of Fully Homomorphic Encryption.
    
  
    IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., June, 2024
    
  
Optimizing Ciphertext Management for Faster Fully Homomorphic Encryption Computation.
    
  
    Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
    
  
  2023
    Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
    
  
  2022
    IEEE Trans. Dependable Secur. Comput., 2022
    
  
    CoRR, 2022
    
  
    Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022
    
  
Accelerating Fully Homomorphic Encryption by Bridging Modular and Bit-Level Arithmetic.
    
  
    Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022
    
  
  2021
    IACR Cryptol. ePrint Arch., 2021
    
  
Fast and Scalable Private Genotype Imputation Using Machine Learning and Partially Homomorphic Encryption.
    
  
    IEEE Access, 2021
    
  
    Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
    
  
  2020
    Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020
    
  
  2019
Experimental Applications on SRAM-Based FPGA for the NanosatC-BR2 Scientific Mission.
    
  
    Proceedings of the IEEE International Parallel and Distributed Processing Symposium Workshops, 2019
    
  
    Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2019
    
  
  2018
    IACR Cryptol. ePrint Arch., 2018
    
  
    Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
    
  
  2017
Analyzing the impact of radiation-induced failures in flash-based APSoC with and without fault tolerance techniques at CERN environment.
    
  
    Microelectron. Reliab., 2017
    
  
  2016
Selective software-implemented hardware fault tolerance tecnhiques to detect soft errors in processors with reduced overhead
    
  
    PhD thesis, 2016
    
  
    Proceedings of the 17th Latin-American Test Symposium, 2016
    
  
  2015
Application-Based Analysis of Register File Criticality for Reliability Assessment in Embedded Microprocessors.
    
  
    J. Electron. Test., 2015
    
  
  2014
    Proceedings of the 24th International Workshop on Power and Timing Modeling, 2014
    
  
    Proceedings of the 15th Latin American Test Workshop, 2014
    
  
  2013
    Proceedings of the 14th Latin American Test Workshop, 2013
    
  
  2012
Configurable tool to protect processors against SEE by software-based detection techniques.
    
  
    Proceedings of the 13th Latin American Test Workshop, 2012
    
  
    Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012
    
  
  2011
    Proceedings of the 12th Latin American Test Workshop, 2011