José Rodrigo Azambuja
Orcid: 0000-0002-2627-5075
According to our database1,
José Rodrigo Azambuja
authored at least 35 papers
between 2007 and 2023.
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Bibliography
2023
Evaluating the Efficiency of Software-only Techniques to Detect SEU and SET in Microprocessors.
CoRR, 2023
Evaluating an XOR-based Hybrid Fault Tolerance Technique to Detect Faults in GPU Pipelines.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023
2022
Evaluating low-level software-based hardening techniques for configurable GPU architectures.
J. Supercomput., 2022
Managing Virtual Programmable Switches: Principles, Requirements, and Design Directions.
IEEE Commun. Mag., 2022
Proceedings of the 2022 IEEE/IFIP Network Operations and Management Symposium, 2022
Video Decoder Improvements with Near-Data Speculative Motion Compensation Processing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Improving Content-Aware Video Streaming in Congested Networks with In-Network Computing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
2021
Toward In-Network Intelligence: Running Distributed Artificial Neural Networks in the Data Plane.
IEEE Commun. Lett., 2021
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021
2020
Proceedings of the SIGCOMM '20: ACM SIGCOMM 2020 Conference, 2020
Evaluating Software-based Hardening Techniques for General-Purpose Registers on a GPGPU.
Proceedings of the IEEE Latin-American Test Symposium, 2020
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020
Investigating Floating-Point Implementations in a Softcore GPU under Radiation-Induced Faults.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020
2019
A Knapsack Methodology for Hardware-based DMR Protection against Soft Errors in Superscalar Out-of-Order Processors.
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019
Proceedings of the ACM SIGCOMM 2019 Conference Posters and Demos, 2019
Proceedings of the IEEE International Parallel and Distributed Processing Symposium Workshops, 2019
Evaluating the Impact of Accuracy Relaxation in the Reliability of GPU Register Files.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
Improving Software-based Techniques for Soft Error Mitigation in OoO Superscalar Processors.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
2018
Evaluating the reliability of a GPU pipeline to SEU and the impacts of software-based and hardware-based fault tolerance techniques.
Microelectron. Reliab., 2018
2017
A low-level software-based fault tolerance approach to detect SEUs in GPUs' register files.
Microelectron. Reliab., 2017
2016
Proceedings of the 17th Latin-American Test Symposium, 2016
2014
Algorithm transformation methods to reduce the overhead of software-based fault tolerance techniques.
Microelectron. Reliab., 2014
Implementation and experimental evaluation of a CUDA core under single event effects.
Proceedings of the 15th Latin American Test Workshop, 2014
2013
Proceedings of the 14th Latin American Test Workshop, 2013
Algorithm transformation methods to reduce software-only fault tolerance techniques' overhead.
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013
2012
Proceedings of the 15th IEEE International Conference on Computational Science and Engineering, 2012
2011
J. Electron. Test., 2011
Using dynamic partial reconfiguration to detect sees in microprocessors through non-intrusive hybrid technique.
Proceedings of the 24th Symposium on Integrated Circuits and Systems Design, 2011
Evaluating the efficiency of data-flow software-based techniques to detect SEEs in microprocessors.
Proceedings of the 12th Latin American Test Workshop, 2011
2010
The limitations of software signature and basic block sizing in soft error fault coverage.
Proceedings of the 11th Latin American Test Workshop, 2010
2009
Evaluating large grain TMR and selective partial reconfiguration for soft error mitigation in SRAM-based FPGAs.
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009
2008
Synchronizing triple modular redundant designs in dynamic partial reconfiguration applications.
Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, 2008
2007
Automatic Generation of Adaptive Multiprocessor Systems.
Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2007