Hervé Yviquel

Orcid: 0000-0003-1214-3431

According to our database1, Hervé Yviquel authored at least 27 papers between 2011 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2023
Source Matching and Rewriting for MLIR Using String-Based Automata.
ACM Trans. Archit. Code Optim., June, 2023

Memory Transfer Decomposition: Exploring Smart Data Movement Through Architecture-Aware Strategies.
Proceedings of the SC '23 Workshops of The International Conference on High Performance Computing, 2023

Towards Fault Tolerance and Resilience in the Sequential Codelet Model.
Proceedings of the High Performance Computing - 10th Latin American Conference, 2023

2022
Source Matching and Rewriting.
CoRR, 2022

Co-optimizing Dataflow Graphs and Actors with MLIR.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2022

Implementing the Broadcast Operation in a Distributed Task-based Runtime.
Proceedings of the International Symposium on Computer Architecture and High Performance Computing Workshops, 2022

An OpenMP-only Linear Algebra Library for Distributed Architectures.
Proceedings of the International Symposium on Computer Architecture and High Performance Computing Workshops, 2022

Ion-Molecule Collision Cross-Section Simulation using Linked-cell and Trajectory Parallelization.
Proceedings of the 2022 IEEE 34th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), 2022

The OpenMP Cluster Programming Model.
Proceedings of the Workshop Proceedings of the 51st International Conference on Parallel Processing, 2022

2021
Enabling OpenMP Task Parallelism on Multi-FPGAs.
Proceedings of the 29th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2021

2020
OmpTracing: Easy Profiling of OpenMP Programs.
Proceedings of the 32nd IEEE International Symposium on Computer Architecture and High Performance Computing, 2020

2018
Cluster Programming using the OpenMP Accelerator Model.
ACM Trans. Archit. Code Optim., 2018

Automatic Ray-Tracer Cloud Offloading in OPENMP.
Proceedings of the 30th International Symposium on Computer Architecture and High Performance Computing, 2018

2017
On the Development and Optimization of HEVC Video Decoders Using High-Level Dataflow Modeling.
J. Signal Process. Syst., 2017

The Cloud as an OpenMP Offloading Device.
Proceedings of the 46th International Conference on Parallel Processing, 2017

2015
Embedded Multi-Core Systems Dedicated to Dynamic Dataflow Programs.
J. Signal Process. Syst., 2015

2014
Efficient software synthesis of dynamic dataflow programs.
Proceedings of the IEEE International Conference on Acoustics, 2014

Orcc's compa-backend demonstration.
Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing, 2014

Development and optimization of high level dataflow programs: The HEVC decoder design case.
Proceedings of the 48th Asilomar Conference on Signals, Systems and Computers, 2014

2013
From dataflow-based video coding tools to dedicated embedded multi-core platforms. (Depuis des outils de codage vidéo basés sur la programmation flux de données vers des plates-formes multi-coeur embarquées et dédiées).
PhD thesis, 2013

Automated design of networks of transport-triggered architecture processors using dynamic dataflow programs.
Signal Process. Image Commun., 2013

Orcc: multimedia development made easy.
Proceedings of the ACM Multimedia Conference, 2013

Towards run-time actor mapping of dynamic dataflow programs onto multi-core platforms.
Proceedings of the 8th International Symposium on Image and Signal Processing and Analysis, 2013

2012
An experimental toolchain based on high-level dataflow models of computation for heterogeneous MPSoC.
Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing, 2012

2011
Efficient multicore scheduling of dataflow process networks.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2011

Just-in-time adaptive decoder engine: a universal video decoder based on MPEG RVC.
Proceedings of the 19th International Conference on Multimedia 2011, Scottsdale, AZ, USA, November 28, 2011

A unified hardware/software co-synthesis solution for signal processing systems.
Proceedings of the 2011 Conference on Design and Architectures for Signal and Image Processing, 2011


  Loading...