Paolo Meloni

Victor Jean-Baptiste Jung

Luca Benini

CoRR, 2024

Exploiting FPGAs and Spiking Neural Networks at the Micro-Edge: The EdgeAI Approach.

[BibT_eX]

[DOI]

Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2024

2023

An Automated Design Flow for Adaptive Neural Network Hardware Accelerators.

[BibT_eX]

[DOI]

J. Signal Process. Syst., September, 2023

A Microcontroller-Based Platform for Cognitive Tracking of Sensorimotor Training.

[BibT_eX]

[DOI]

Bojan Blazica

IEEE Access, 2023

On-FPGA Spiking Neural Networks for End-to-End Neural Decoding.

[BibT_eX]

[DOI]

Gianluca Leone

IEEE Access, 2023

Spiking Neural Networks for Integrated Reach-to-Grasp Decoding on FPGAs.

[BibT_eX]

[DOI]

Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2023

On-FPGA Spiking Neural Networks for Multi-variable End-to-End Neural Decoding.

[BibT_eX]

[DOI]

Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2023

2022

An Adaptive Cognitive Sensor Node for ECG Monitoring in the Internet of Medical Things.

[BibT_eX]

[DOI]

Daniela Loi

IEEE Access, 2022

A Bandwidth-Efficient Emulator of Biologically-Relevant Spiking Neural Networks on FPGA.

[BibT_eX]

[DOI]

Gianluca Leone

IEEE Access, 2022

Target-Aware Neural Architecture Search and Deployment for Keyword Spotting.

[BibT_eX]

[DOI]

IEEE Access, 2022

Integration of Energy Storage Systems within Modular Multilevel Converters for Medium-Voltage Distribution Networks.

[BibT_eX]

[DOI]

Alessandro Serpi

Proceedings of the IECON 2022, 2022

An Adaptable Cognitive Microcontroller Node for Fitness Activity Recognition.

[BibT_eX]

[DOI]

Bojan Blazica

Proceedings of the Design and Architecture for Signal and Image Processing, 2022

Dynamic Pruning for Parsimonious CNN Inference on Embedded Systems.

[BibT_eX]

[DOI]

Paola Busia

Vasileios K. Pothos

Nikos Fragoulis

Proceedings of the Design and Architecture for Signal and Image Processing, 2022

EEGformer: Transformer-Based Epilepsy Detection on Raw EEG Traces for Low-Channel-Count Wearable Continuous Monitoring Devices.

[BibT_eX]

[DOI]

Paola Busia

Andrea Cossettini

Thorir Mar Ingolfsson

Simone Benatti

Alessio Burrello

Moritz Scherer

Luca Benini

Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2022

2021

Proceedings of the DATE Friday Workshop on System-level Design Methods for Deep Learning on Heterogeneous Architectures (SLOHA 2021).

[BibT_eX]

[DOI]

CoRR, 2021

ALOHA: A Unified Platform-Aware Evaluation Method for CNNs Execution on Heterogeneous Systems at the Edge.

[BibT_eX]

[DOI]

IEEE Access, 2021

Task-Specific Automation in Deep Learning Processes.

[BibT_eX]

[DOI]

Georg Buchgeher

Gerald Czech

Adriano Souza Ribeiro

Proceedings of the Database and Expert Systems Applications - DEXA 2021 Workshops, 2021

2020

Optimizing Temporal Convolutional Network Inference on FPGA-Based Accelerators.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2020

Exploring NEURAghe: A Customizable Template for APSoC-Based CNN Inference at the Edge.

[BibT_eX]

[DOI]

IEEE Embed. Syst. Lett., 2020

ZyON: Enabling Spike Sorting on APSoC-Based Signal Processors for High-Density Microelectrode Arrays.

[BibT_eX]

[DOI]

Gianluca Leone

IEEE Access, 2020

Biosensing IoT Platform for Water Management in Vineyards.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019

A Closed-Loop System Processing High-Density Electrical Recordings and Visual Stimuli to Study Retinal Circuits Properties.

[BibT_eX]

[DOI]

Proceedings of the 2019 9th International IEEE/EMBS Conference on Neural Engineering (NER), 2019

CNN hardware acceleration on a low-power and low-cost APSoC.

[BibT_eX]

[DOI]

Proceedings of the 2019 Conference on Design and Architectures for Signal and Image Processing, 2019

Runtime-Adaptive Cognitive IoT Nodes.

[BibT_eX]

[DOI]

Daniela Loi

Proceedings of the Cyber-Physical Systems PhD Workshop 2019, an event held within the CPS Summer School "Designing Cyber-Physical Systems, 2019

Flexible Acceleration of Convolutions on FPGAs: NEURAghe 2.0.

[BibT_eX]

[DOI]

Marco Carreras

Gianfranco Deriu

Proceedings of the Cyber-Physical Systems PhD Workshop 2019, an event held within the CPS Summer School "Designing Cyber-Physical Systems, 2019

A runtime-adaptive cognitive IoT node for healthcare monitoring.

[BibT_eX]

[DOI]

Daniela Loi

Proceedings of the 16th ACM International Conference on Computing Frontiers, 2019

Optimization and deployment of CNNs at the edge: the ALOHA experience.

[BibT_eX]

[DOI]

Michael Masin

Francesca Palumbo

Proceedings of the 16th ACM International Conference on Computing Frontiers, 2019

2018

NEURAghe: Exploiting CPU-FPGA Synergies for Efficient and Flexible CNN Inference Acceleration on Zynq SoCs.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2018

Exploiting All Programmable SoCs in Neural Signal Analysis: A Closed-Loop Control for Large-Scale CMOS Multielectrode Arrays.

[BibT_eX]

[DOI]

IEEE Trans. Biomed. Circuits Syst., 2018

Architecture-aware design and implementation of CNN algorithms for embedded inference: the ALOHA project.

[BibT_eX]

[DOI]

Proceedings of the 30th International Conference on Microelectronics, 2018

ALOHA: an architectural-aware framework for deep learning at the edge.

[BibT_eX]

[DOI]

Prasanth Kuncheerath Ramankutty

Michael Masin

Francesca Palumbo

Proceedings of the Workshop on INTelligent Embedded Systems Architectures and Applications, 2018

2017

Power-Awarness in Coarse-Grained Reconfigurable Multi-Functional Architectures: a Dataflow Based Strategy.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2017

Real-Time neural signal decoding on heterogeneous MPSocs based on VLIW ASIPs.

[BibT_eX]

[DOI]

J. Syst. Archit., 2017

Challenging the Best HEVC Fractional Pixel FPGA Interpolators With Reconfigurable and Multifrequency Approximate Computing.

[BibT_eX]

[DOI]

IEEE Embed. Syst. Lett., 2017

On-FPGA Real-Time Processing of Biological Signals From High-Density MEAs: a Design Space Exploration.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, 2017

Feasibility Study of Real-Time Spiking Neural Network Simulations on a Swarm Intelligence Based Digital Architecture.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, 2017

2016

Automated Design Flow for Multi-Functional Dataflow-Based Platforms.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2016

On-the-fly adaptivity for process networks over shared-memory platforms.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2016

MPSoCs for real-time neural signal decoding: A low-power ASIP-based implementation.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2016

Modelling and Automated Implementation of Optimal Power Saving Strategies in Coarse-Grained Reconfigurable Architectures.

[BibT_eX]

[DOI]

J. Electr. Comput. Eng., 2016

Dataflow-Based Design of Coarse-Grained Reconfigurable Platforms.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Workshop on Signal Processing Systems, 2016

A high-efficiency runtime reconfigurable IP for CNN acceleration on a mid-range all-programmable SoC.

[BibT_eX]

[DOI]

Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016

Demo: Reconfigurable Platform Composer Tool.

[BibT_eX]

[DOI]

Proceedings of the 2016 Conference on Design and Architectures for Signal and Image Processing (DASIP), 2016

Curbing the roofline: a scalable and flexible architecture for CNNs on FPGA.

[BibT_eX]

[DOI]

Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016

Power and clock gating modelling in coarse grained reconfigurable systems.

[BibT_eX]

[DOI]

Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016

2015

Reconfigurable coprocessors synthesis in the MPEG-RVC domain.

[BibT_eX]

[DOI]

Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

Power modelling for saving strategies in coarse grained reconfigurable systems.

[BibT_eX]

[DOI]

Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

Exploring custom heterogeneous MPSoCs for real-time neural signal decoding.

[BibT_eX]

[DOI]

Proceedings of the 2015 Conference on Design and Architectures for Signal and Image Processing, 2015

2014

The multi-dataflow composer tool: generation of on-the-fly reconfigurable platforms.

[BibT_eX]

[DOI]

J. Real Time Image Process., 2014

A Custom MPSoC Architecture With Integrated Power Management for Real-Time Neural Signal Decoding.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2014

Online process transformation for polyhedral process networks in shared-memory MPSoCs.

[BibT_eX]

[DOI]

Proceedings of the 3rd Mediterranean Conference on Embedded Computing, 2014

A Stream Buffer Mechanism for Pervasive Splitting Transformations on Polyhedral Process Networks.

[BibT_eX]

[DOI]

Proceedings of the 2nd International Workshop on Many-core Embedded Systems, 2014

2013

ASAM: Automatic architecture synthesis and application mapping.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2013

A system-level approach to adaptivity and fault-tolerance in NoC-based MPSoCs: The MADNESS project.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2013

A Low Overhead Self-adaptation Technique for KPN Applications on NoC-based MPSoCs.

[BibT_eX]

Onur Derin

Giuseppe Tuveri

Proceedings of the PECCS 2013, 2013

A runtime adaptive H.264 video-decoding MPSoC platform.

[BibT_eX]

[DOI]

Proceedings of the 2013 Conference on Design and Architectures for Signal and Image Processing, 2013

Welcome to the 2013 conference on design and architectures for signal and image processing (DASIP) in Cagliari, Italy.

[BibT_eX]

[DOI]

Prasanth Kuncheerath Ramankutty

Christophe Jégo

Proceedings of the 2013 Conference on Design and Architectures for Signal and Image Processing, 2013

2012

Enabling Fast ASIP Design Space Exploration: An FPGA-Based Runtime Reconfigurable Prototyper.

[BibT_eX]

[DOI]

VLSI Design, 2012

Adaptivity Support for MPSoCs Based on Process Migration in Polyhedral Process Networks.

[BibT_eX]

[DOI]

VLSI Design, 2012

Towards Self-Adaptive KPN Applications on NoC-Based MPSoCs.

[BibT_eX]

[DOI]

Onur Derin

Emanuele Cannella

Adv. Softw. Eng., 2012

Combining on-hardware prototyping and high-level simulation for DSE of multi-ASIP systems.

[BibT_eX]

[DOI]

Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012

System Adaptivity and Fault-Tolerance in NoC-based MPSoCs: The MADNESS Project Approach.

[BibT_eX]

[DOI]

Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

ASAM: Automatic Architecture Synthesis and Application Mapping.

[BibT_eX]

[DOI]

Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Exploiting binary translation for fast ASIP design space exploration on FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011

Towards an ESL design framework for adaptive and fault-tolerant MPSoCs: MADNESS or not?

[BibT_eX]

[DOI]

Proceedings of the 9th IEEE Symposium on Embedded Systems for Real-Time Multimedia, 2011

2010

An FPGA-Based Framework for Technology-Aware Prototyping of Multicore Embedded Architectures.

[BibT_eX]

[DOI]

Simone Secchi

IEEE Embed. Syst. Lett., 2010

Enabling fast Network-on-Chip topology selection: an FPGA-based runtime reconfigurable prototyper.

[BibT_eX]

[DOI]

Simone Secchi

Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

Exploiting FPGAs for technology-aware system-level evaluation of multi-core architectures.

[BibT_eX]

[DOI]

Simone Secchi