Paolo Meloni

According to our database1, Paolo Meloni authored at least 56 papers between 2005 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2019
A Closed-Loop System Processing High-Density Electrical Recordings and Visual Stimuli to Study Retinal Circuits Properties.
Proceedings of the 2019 9th International IEEE/EMBS Conference on Neural Engineering (NER), 2019

Runtime-Adaptive Cognitive IoT Nodes.
Proceedings of the Cyber-Physical Systems PhD Workshop 2019, an event held within the CPS Summer School "Designing Cyber-Physical Systems, 2019

Flexible Acceleration of Convolutions on FPGAs: NEURAghe 2.0.
Proceedings of the Cyber-Physical Systems PhD Workshop 2019, an event held within the CPS Summer School "Designing Cyber-Physical Systems, 2019

A runtime-adaptive cognitive IoT node for healthcare monitoring.
Proceedings of the 16th ACM International Conference on Computing Frontiers, 2019

Optimization and deployment of CNNs at the edge: the ALOHA experience.
Proceedings of the 16th ACM International Conference on Computing Frontiers, 2019

2018
NEURAghe: Exploiting CPU-FPGA Synergies for Efficient and Flexible CNN Inference Acceleration on Zynq SoCs.
TRETS, 2018

Exploiting All Programmable SoCs in Neural Signal Analysis: A Closed-Loop Control for Large-Scale CMOS Multielectrode Arrays.
IEEE Trans. Biomed. Circuits and Systems, 2018

ALOHA: an architectural-aware framework for deep learning at the edge.
Proceedings of the Workshop on INTelligent Embedded Systems Architectures and Applications, 2018

2017
Power-Awarness in Coarse-Grained Reconfigurable Multi-Functional Architectures: a Dataflow Based Strategy.
Signal Processing Systems, 2017

Real-Time neural signal decoding on heterogeneous MPSocs based on VLIW ASIPs.
Journal of Systems Architecture - Embedded Systems Design, 2017

Challenging the Best HEVC Fractional Pixel FPGA Interpolators With Reconfigurable and Multifrequency Approximate Computing.
Embedded Systems Letters, 2017

On-FPGA Real-Time Processing of Biological Signals From High-Density MEAs: a Design Space Exploration.
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, 2017

Feasibility Study of Real-Time Spiking Neural Network Simulations on a Swarm Intelligence Based Digital Architecture.
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, 2017

2016
Automated Design Flow for Multi-Functional Dataflow-Based Platforms.
Signal Processing Systems, 2016

On-the-fly adaptivity for process networks over shared-memory platforms.
Microprocessors and Microsystems - Embedded Hardware Design, 2016

MPSoCs for real-time neural signal decoding: A low-power ASIP-based implementation.
Microprocessors and Microsystems - Embedded Hardware Design, 2016

Modelling and Automated Implementation of Optimal Power Saving Strategies in Coarse-Grained Reconfigurable Architectures.
J. Electrical and Computer Engineering, 2016

Dataflow-Based Design of Coarse-Grained Reconfigurable Platforms.
Proceedings of the 2016 IEEE International Workshop on Signal Processing Systems, 2016

A high-efficiency runtime reconfigurable IP for CNN acceleration on a mid-range all-programmable SoC.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016

Demo: Reconfigurable Platform Composer Tool.
Proceedings of the 2016 Conference on Design and Architectures for Signal and Image Processing (DASIP), 2016

Curbing the roofline: a scalable and flexible architecture for CNNs on FPGA.
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016

Power and clock gating modelling in coarse grained reconfigurable systems.
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016

2015
Reconfigurable coprocessors synthesis in the MPEG-RVC domain.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

Power modelling for saving strategies in coarse grained reconfigurable systems.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

Exploring custom heterogeneous MPSoCs for real-time neural signal decoding.
Proceedings of the 2015 Conference on Design and Architectures for Signal and Image Processing, 2015

2014
The multi-dataflow composer tool: generation of on-the-fly reconfigurable platforms.
J. Real-Time Image Processing, 2014

A Custom MPSoC Architecture With Integrated Power Management for Real-Time Neural Signal Decoding.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2014

A Stream Buffer Mechanism for Pervasive Splitting Transformations on Polyhedral Process Networks.
Proceedings of the 2nd International Workshop on Many-core Embedded Systems, 2014

2013
ASAM: Automatic architecture synthesis and application mapping.
Microprocessors and Microsystems - Embedded Hardware Design, 2013

A system-level approach to adaptivity and fault-tolerance in NoC-based MPSoCs: The MADNESS project.
Microprocessors and Microsystems - Embedded Hardware Design, 2013

A Low Overhead Self-adaptation Technique for KPN Applications on NoC-based MPSoCs.
Proceedings of the PECCS 2013, 2013

A runtime adaptive H.264 video-decoding MPSoC platform.
Proceedings of the 2013 Conference on Design and Architectures for Signal and Image Processing, 2013

Welcome to the 2013 conference on design and architectures for signal and image processing (DASIP) in Cagliari, Italy.
Proceedings of the 2013 Conference on Design and Architectures for Signal and Image Processing, 2013

2012
Enabling Fast ASIP Design Space Exploration: An FPGA-Based Runtime Reconfigurable Prototyper.
VLSI Design, 2012

Adaptivity Support for MPSoCs Based on Process Migration in Polyhedral Process Networks.
VLSI Design, 2012

Towards Self-Adaptive KPN Applications on NoC-Based MPSoCs.
Adv. Software Engineering, 2012

Combining on-hardware prototyping and high-level simulation for DSE of multi-ASIP systems.
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012

System Adaptivity and Fault-Tolerance in NoC-based MPSoCs: The MADNESS Project Approach.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

ASAM: Automatic Architecture Synthesis and Application Mapping.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Exploiting binary translation for fast ASIP design space exploration on FPGAs.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011
Towards an ESL design framework for adaptive and fault-tolerant MPSoCs: MADNESS or not?
Proceedings of the 9th IEEE Symposium on Embedded Systems for Real-Time Multimedia, 2011

2010
An FPGA-Based Framework for Technology-Aware Prototyping of Multicore Embedded Architectures.
Embedded Systems Letters, 2010

Enabling fast Network-on-Chip topology selection: an FPGA-based runtime reconfigurable prototyper.
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

Exploiting FPGAs for technology-aware system-level evaluation of multi-core architectures.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2010

2007
Area and Power Modeling for Networks-on-Chip with Layout Awareness.
VLSI Design, 2007

Synthesis of Predictable Networks-on-Chip-Based Interconnect Architectures for Chip Multiprocessors.
IEEE Trans. VLSI Syst., 2007

A Layout-Aware Analysis of Networks-on-Chip and Traditional Interconnects for MPSoCs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

NoC Design and Implementation in 65nm Technology.
Proceedings of the First International Symposium on Networks-on-Chips, 2007

On the impact of serialization on the cache performances in Network-on-Chip based MPSoCs.
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

2006
Designing Routing and Message-Dependent Deadlock Free Networks on Chips.
Proceedings of the VLSI-SoC: Research Trends in VLSI and Systems on Chip, 2006

Designing Message-Dependent Deadlock Free Networks on Chips for Application-Specific Systems on Chips.
Proceedings of the IFIP VLSI-SoC 2006, 2006

Routing Aware Switch Hardware Customization for Networks on Chips.
Proceedings of the 1st International ICST Conference on Nano-Networks, 2006

Area and Power Modeling Methodologies for Networks-on-Chip.
Proceedings of the 1st International ICST Conference on Nano-Networks, 2006

Designing application-specific networks on chips with floorplan information.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Contrasting a NoC and a traditional interconnect fabric with layout awareness.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005
Networks on Chips: A Synthesis Perspective.
Proceedings of the Parallel Computing: Current & Future Issues of High-End Computing, 2005


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