Luigi Raffo

According to our database1, Luigi Raffo authored at least 120 papers between 1990 and 2018.

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Bibliography

2018
Exploiting All Programmable SoCs in Neural Signal Analysis: A Closed-Loop Control for Large-Scale CMOS Multielectrode Arrays.
IEEE Trans. Biomed. Circuits and Systems, 2018

Automatic Recognition of Complete Atrioventricular Activity in Fetal Pulsed-Wave Doppler Signals.
Proceedings of the 40th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2018

Adaptive Filtering for Electromyographic Signal Processing in Scoliosis Indexes Estimation.
Proceedings of the 11th International Joint Conference on Biomedical Engineering Systems and Technologies (BIOSTEC 2018), 2018

Impact of a TV-based Assistive Technology on Older People's Ability to Self-manage Their Own Health.
Proceedings of the 11th International Joint Conference on Biomedical Engineering Systems and Technologies (BIOSTEC 2018), 2018

2017
A Precision Pseudo Resistor Bias Scheme for the Design of Very Large Time Constant Filters.
IEEE Trans. on Circuits and Systems, 2017

Real-Time neural signal decoding on heterogeneous MPSocs based on VLIW ASIPs.
Journal of Systems Architecture - Embedded Systems Design, 2017

Hardware design methodology using lightweight dataflow and its integration with low power techniques.
Journal of Systems Architecture - Embedded Systems Design, 2017

Challenging the Best HEVC Fractional Pixel FPGA Interpolators With Reconfigurable and Multifrequency Approximate Computing.
Embedded Systems Letters, 2017

NEURAghe: Exploiting CPU-FPGA Synergies for Efficient and Flexible CNN Inference Acceleration on Zynq SoCs.
CoRR, 2017

A Novel Embedded System for Direct, Programmable Stimulation of the Peripheral Neural System.
Proceedings of the New Generation of CAS, 2017

On-FPGA Real-Time Processing of Biological Signals From High-Density MEAs: a Design Space Exploration.
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, 2017

Feasibility Study of Real-Time Spiking Neural Network Simulations on a Swarm Intelligence Based Digital Architecture.
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, 2017

A 64-channels neural interface for biopotentials recording and PNS stimulation.
Proceedings of the 2017 39th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), 2017

Comparative evaluation of different wavelet thresholding methods for neural signal processing.
Proceedings of the 2017 39th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), 2017

Cross-layer design of reconfigurable cyber-physical systems.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

EARNEST: A 64 channel device for neural recording and sensory touch restoration in neural prosthetics.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017

Challenging CPS Trade-off Adaptivity with Coarse-Grained Reconfiguration.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2017

2016
Automated Design Flow for Multi-Functional Dataflow-Based Platforms.
Signal Processing Systems, 2016

Early Stage Automatic Strategy for Power-Aware Signal Processing Systems Design.
Signal Processing Systems, 2016

On-the-fly adaptivity for process networks over shared-memory platforms.
Microprocessors and Microsystems - Embedded Hardware Design, 2016

MPSoCs for real-time neural signal decoding: A low-power ASIP-based implementation.
Microprocessors and Microsystems - Embedded Hardware Design, 2016

Modelling and Automated Implementation of Optimal Power Saving Strategies in Coarse-Grained Reconfigurable Architectures.
J. Electrical and Computer Engineering, 2016

Dataflow-Based Design of Coarse-Grained Reconfigurable Platforms.
Proceedings of the 2016 IEEE International Workshop on Signal Processing Systems, 2016

A high-efficiency runtime reconfigurable IP for CNN acceleration on a mid-range all-programmable SoC.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016

Coarse grain reconfiguration: Power estimation and management flow for hybrid gated systems.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016

Investigation on the hermeticity of an implantable package with 32 feedthroughs for neural prosthetic applications.
Proceedings of the 38th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2016

Demo: Reconfigurable Platform Composer Tool.
Proceedings of the 2016 Conference on Design and Architectures for Signal and Image Processing (DASIP), 2016

Low power design methodology for signal processing systems using lightweight dataflow techniques.
Proceedings of the 2016 Conference on Design and Architectures for Signal and Image Processing (DASIP), 2016

The HEREiAM Tele-social-care Platform for Collaborative Management of Independent Living.
Proceedings of the 2016 International Conference on Collaboration Technologies and Systems, 2016

Curbing the roofline: a scalable and flexible architecture for CNNs on FPGA.
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016

Power and clock gating modelling in coarse grained reconfigurable systems.
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016

Adaptable AES implementation with power-gating support.
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016

2015
An HV-CMOS Integrated Circuit for Neural Stimulation in Prosthetic Applications.
IEEE Trans. on Circuits and Systems, 2015

Computing Swarms for Self-Adaptiveness and Self-Organization in Floating-Point Array Processing.
TAAS, 2015

Coarse-grained reconfiguration: dataflow-based power management.
IET Computers & Digital Techniques, 2015

The challenge of collaborative telerehabilitation: conception and evaluation of a telehealth system enhancement for home-therapy follow-up.
Concurrency and Computation: Practice and Experience, 2015

Toward the Development of a Neuro-Controlled Bidirectional Hand Prosthesis.
Proceedings of the Symbiotic Interaction - 4th International Workshop, 2015

Reconfigurable coprocessors synthesis in the MPEG-RVC domain.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

Power modelling for saving strategies in coarse grained reconfigurable systems.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

Home telemonitoring of vital signs through a TV-based application for elderly patients.
Proceedings of the 2015 IEEE International Symposium on Medical Measurements and Applications, 2015

A configurable biopotentials acquisition module suitable for fetal electrocardiography studies.
Proceedings of the 2015 IEEE International Symposium on Medical Measurements and Applications, 2015

A TV-based ICT Platform for Active Ageing, Tele-care and Social Networking.
Proceedings of the ICT4AgeingWell 2015, 2015

Exploring custom heterogeneous MPSoCs for real-time neural signal decoding.
Proceedings of the 2015 Conference on Design and Architectures for Signal and Image Processing, 2015

Automated power gating methodology for dataflow-based reconfigurable systems.
Proceedings of the 12th ACM International Conference on Computing Frontiers, 2015

2014
Real-time blind audio source separation: performance assessment on an advanced digital signal processor.
The Journal of Supercomputing, 2014

The multi-dataflow composer tool: generation of on-the-fly reconfigurable platforms.
J. Real-Time Image Processing, 2014

A Custom MPSoC Architecture With Integrated Power Management for Real-Time Neural Signal Decoding.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2014

Power-awarness in coarse-grained reconfigurable designs: A dataflow based strategy.
Proceedings of the 2014 IEEE Workshop on Signal Processing Systems, 2014

Automated design flow for coarse-grained reconfigurable platforms: An RVC-CAL multi-standard decoder use-case.
Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014

A Stream Buffer Mechanism for Pervasive Splitting Transformations on Polyhedral Process Networks.
Proceedings of the 2nd International Workshop on Many-core Embedded Systems, 2014

VLSI Wavelet Denoising of Neural Signals - Critical Appraisal of Different Algorithmic Solutions for Threshold Estimation.
Proceedings of the BIODEVICES 2014, 2014

2013
ASAM: Automatic architecture synthesis and application mapping.
Microprocessors and Microsystems - Embedded Hardware Design, 2013

A system-level approach to adaptivity and fault-tolerance in NoC-based MPSoCs: The MADNESS project.
Microprocessors and Microsystems - Embedded Hardware Design, 2013

DSE and profiling of multi-context coarse-grained reconfigurable systems.
Proceedings of the 8th International Symposium on Image and Signal Processing and Analysis, 2013

A runtime adaptive H.264 video-decoding MPSoC platform.
Proceedings of the 2013 Conference on Design and Architectures for Signal and Image Processing, 2013

A coarse-grained reconfigurable wavelet denoiser exploiting the Multi-Dataflow Composer tool.
Proceedings of the 2013 Conference on Design and Architectures for Signal and Image Processing, 2013

A collaborative approach to the telerehabilitation of patients with hand impairments.
Proceedings of the 2013 International Conference on Collaboration Technologies and Systems, 2013

Exploring hardware support for scaling irregular applications on multi-node multi-core architectures.
Proceedings of the 24th International Conference on Application-Specific Systems, 2013

2012
Enabling Fast ASIP Design Space Exploration: An FPGA-Based Runtime Reconfigurable Prototyper.
VLSI Design, 2012

Combining on-hardware prototyping and high-level simulation for DSE of multi-ASIP systems.
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012

Multi-purpose systems: A novel dataflow-based generation and mapping strategy.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

System Adaptivity and Fault-Tolerance in NoC-based MPSoCs: The MADNESS Project Approach.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

ASAM: Automatic Architecture Synthesis and Application Mapping.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Exploiting binary translation for fast ASIP design space exploration on FPGAs.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

A nature-inspired adaptive floating-point coprocessing system.
Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing, 2012

Concurrent hybrid switching for massively parallel systems-on-chip: the CYBER architecture.
Proceedings of the Computing Frontiers Conference, CF'12, 2012

A Portable Real-time Monitoring System for Kinesitherapic Hand Rehabilitation Exercises.
Proceedings of the BIODEVICES 2012 - Proceedings of the International Conference on Biomedical Electronics and Devices, Vilamoura, Algarve, Portugal, 1, 2012

2011
Peripheral Neural Activity Recording and Stimulation System.
IEEE Trans. Biomed. Circuits and Systems, 2011

The Multi-Dataflow Composer tool: A runtime reconfigurable HDL platform composer.
Proceedings of the 2011 Conference on Design and Architectures for Signal and Image Processing, 2011

KeepInTouch: A telehealth system to improve the follow-up of chronic patients.
Proceedings of the 2011 International Conference on Collaboration Technologies and Systems, 2011

Towards self-adaptive networks on chip for massively parallel processors: multilevel quality of service programmability.
Proceedings of the 8th Conference on Computing Frontiers, 2011

2010
Self-coordinated On-Chip Parallel Computing: A Swarm Intelligence Approach.
Proceedings of the Parallel and Distributed Computational Intelligence, 2010

A fast MPI-based parallel framework for cycle-accurate HDL multi-parametric simulations.
IJHPSA, 2010

An FPGA-Based Framework for Technology-Aware Prototyping of Multicore Embedded Architectures.
Embedded Systems Letters, 2010

Enabling fast Network-on-Chip topology selection: an FPGA-based runtime reconfigurable prototyper.
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

Impact of Half-Duplex and Full-Duplex DMA Implementations on NoC Performance.
Proceedings of the NOCS 2010, 2010

Exploiting FPGAs for technology-aware system-level evaluation of multi-core architectures.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2010

RVC: A multi-decoder CAL Composer tool.
Proceedings of the 2010 Conference on Design & Architectures for Signal & Image Processing, 2010

Self organization on a swarm computing fabric: a new way to look at fault tolerance.
Proceedings of the 7th Conference on Computing Frontiers, 2010

2008
A Novel Non-exclusive Dual-Mode Architecture for MPSoCs-Oriented Network on Chip Designs.
Proceedings of the Embedded Computer Systems: Architectures, 2008

A pervasive telemedicine system exploiting the DVB-T technology.
Proceedings of the 2nd International ICST Conference on Pervasive Computing Technologies for Healthcare, 2008

A Network on Chip Architecture for Heterogeneous Traffic Support with Non-Exclusive Dual-Mode Switching.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

Non-Invasive Real-Time Fetal ECG Extraction - A Block-on-Line DSP Implementation based on the JADE Algorithm.
Proceedings of the First International Conference on Biomedical Electronics and Devices, 2008

A DVB-T Based System for the Diffusion of Tele-Home Care Practice.
Proceedings of the First International Conference on Health Informatics, 2008

2007
A Surface Tension and Coalescence Model for Dynamic Distributed Resources Allocation in Massively Parallel Processors on-Chip.
Proceedings of the Nature Inspired Cooperative Strategies for Optimization (NICSO 2007), 2007

Self-Organization on Silicon: System Integration of a Fixed-Point Swarm Coprocessor.
Proceedings of the Nature Inspired Cooperative Strategies for Optimization (NICSO 2007), 2007

Area and Power Modeling for Networks-on-Chip with Layout Awareness.
VLSI Design, 2007

Synthesis of Predictable Networks-on-Chip-Based Interconnect Architectures for Chip Multiprocessors.
IEEE Trans. VLSI Syst., 2007

A Layout-Aware Analysis of Networks-on-Chip and Traditional Interconnects for MPSoCs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

NoC Design and Implementation in 65nm Technology.
Proceedings of the First International Symposium on Networks-on-Chips, 2007

On the impact of serialization on the cache performances in Network-on-Chip based MPSoCs.
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

2006
Reconfigurable Coprocessor for Multimedia Application Domain.
VLSI Signal Processing, 2006

Stigmergic approaches applied to flexible fault-tolerant digital VLSI architectures.
J. Parallel Distrib. Comput., 2006

Designing Routing and Message-Dependent Deadlock Free Networks on Chips.
Proceedings of the VLSI-SoC: Research Trends in VLSI and Systems on Chip, 2006

Designing Message-Dependent Deadlock Free Networks on Chips for Application-Specific Systems on Chips.
Proceedings of the IFIP VLSI-SoC 2006, 2006

Routing Aware Switch Hardware Customization for Networks on Chips.
Proceedings of the 1st International ICST Conference on Nano-Networks, 2006

Area and Power Modeling Methodologies for Networks-on-Chip.
Proceedings of the 1st International ICST Conference on Nano-Networks, 2006

Designing application-specific networks on chips with floorplan information.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Automatic Application Partitioning on FPGA/CPU Systems Based on Detailed Low-Level Information.
Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

Contrasting a NoC and a traditional interconnect fabric with layout awareness.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Cooperative VLSI Tiled Architectures: Stigmergy in a Swarm Coprocessor.
Proceedings of the Ant Colony Optimization and Swarm Intelligence, 2006

2005
A Low-Power Integrated Smart Sensor with on-Chip Real-Time Image Processing Capabilities.
EURASIP J. Adv. Sig. Proc., 2005

Networks on Chips: A Synthesis Perspective.
Proceedings of the Parallel Computing: Current & Future Issues of High-End Computing, 2005

Run-time Adaptive Resources Allocation and Balancing on Nanoprocessors Arrays.
Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005

xpipes Lite: A Synthesis Oriented Design Library For Networks on Chips.
Proceedings of the 2005 Design, 2005

2004
A Swarm Intelligence Based VLSI Multiplication-and-Add Scheme.
Proceedings of the Parallel Problem Solving from Nature, 2004

A VLSI Multiplication-and-Add Scheme Based on Swarm Intelligence Approaches.
Proceedings of the Ant Colony Optimization and Swarm Intelligence, 2004

2000
A micro-power mixed signal IC for battery-operated burglar alarm systems.
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000

1999
A modular digital VLSI architecture for stereo depth estimation in industrial applications.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

1998
Analog VLSI circuits as physical structures for perception in early visual tasks.
IEEE Trans. Neural Networks, 1998

Analogue VLSI primitives for perceptual tasks in machine vision.
Neural Computing and Applications, 1998

Analog computation for phase-based disparity estimation: continuous and discrete models.
Mach. Vis. Appl., 1998

1997
Design of an ASIP architecture for low-level visual elaborations.
IEEE Trans. VLSI Syst., 1997

Functional Periodic Intracortical Couplings Induced by Structured Lateral Inhibition in a Linear Cortical Network.
Neural Computation, 1997

An Analog VLSI Computational Engine for Early Vision Tasks.
Proceedings of the Artificial Neural Networks, 1997

1996
A VLSI Image Processing Architecture Dedicated to Real-Time Quality Control Analysis in an Industrial Plant.
Real-Time Imaging, 1996

A recurrent neural architecture mimicking cortical preattentive vision systems.
Neurocomputing, 1996

A programmable VLSI architecture based on multilayer CNN paradigms for real-time visual processing.
I. J. Circuit Theory and Applications, 1996

1995
A neuromorphic architecture for cortical multilayer integration of early visual tasks.
Mach. Vis. Appl., 1995

1990
Pre-placement of VLSI blocks through learning neural networks.
Proceedings of the European Design Automation Conference, 1990


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