Luigi Raffo
Orcid: 0000-0001-9683-009XAffiliations:
- University of Cagliari, Italy
According to our database1,
Luigi Raffo
authored at least 164 papers
between 1990 and 2023.
Collaborative distances:
Collaborative distances:
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Bibliography
2023
J. Signal Process. Syst., September, 2023
IEEE Access, 2023
Arrhythmogenic Sites Mapping in Post-Ischemic Ventricular Tachycardia Using a Siamese Neural Network.
Proceedings of the Computing in Cardiology, 2023
Proceedings of the 20th ACM International Conference on Computing Frontiers, 2023
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2023
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2023
2022
An Adaptive Cognitive Sensor Node for ECG Monitoring in the Internet of Medical Things.
IEEE Access, 2022
A Bandwidth-Efficient Emulator of Biologically-Relevant Spiking Neural Networks on FPGA.
IEEE Access, 2022
IEEE Access, 2022
Proceedings of the 13th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 11th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, 2022
Proceedings of the Computing in Cardiology, 2022
2021
The Multi-Dataflow Composer tool: An open-source tool suite for optimized coarse-grain reconfigurable hardware accelerators and platform design.
Microprocess. Microsystems, 2021
CoRR, 2021
ALOHA: A Unified Platform-Aware Evaluation Method for CNNs Execution on Heterogeneous Systems at the Edge.
IEEE Access, 2021
2020
ACM Trans. Design Autom. Electr. Syst., 2020
Design and Usability Assessment of a Multi-Device SOA-Based Telecare Framework for the Elderly.
IEEE J. Biomed. Health Informatics, 2020
IEEE J. Emerg. Sel. Topics Circuits Syst., 2020
Automatic detection of complete and measurable cardiac cycles in antenatal pulsed-wave Doppler signals.
Comput. Methods Programs Biomed., 2020
Wavelet denoising as a post-processing enhancement method for non-invasive foetal electrocardiography.
Comput. Methods Programs Biomed., 2020
IEEE Access, 2020
ZyON: Enabling Spike Sorting on APSoC-Based Signal Processors for High-Density Microelectrode Arrays.
IEEE Access, 2020
Proceedings of the 2020 IEEE International Symposium on Medical Measurements and Applications, 2020
A Novel Tool for Non-Invasive Fetal Electrocardiography Research: the NInFEA Dataset.
Proceedings of the 42nd Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2020
2019
J. Syst. Archit., 2019
Dataflow-Functional High-Level Synthesis for Coarse-Grained Reconfigurable Accelerators.
IEEE Embed. Syst. Lett., 2019
Reconfigurable Adaptive Multiple Transform Hardware Solutions for Versatile Video Coding.
IEEE Access, 2019
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2019
Comparison of Single- and Multi-reference QRD-RLS adaptive filter for non-invasive fetal electrocardiography.
Proceedings of the 41st Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2019
Proceedings of the Cyber-Physical Systems PhD Workshop 2019, an event held within the CPS Summer School "Designing Cyber-Physical Systems, 2019
Proceedings of the 46th Computing in Cardiology, 2019
Proceedings of the 16th ACM International Conference on Computing Frontiers, 2019
CERBERO: Cross-layer modEl-based fRamework for multi-oBjective dEsign of reconfigurable systems in unceRtain hybRid envirOnments: Invited paper: CERBERO teams from UniSS, UniCA, IBM Research, TASE, INSA-Rennes, UPM, USI, Abinsula, AmbieSense, TNO, S&T, CRF.
Proceedings of the 16th ACM International Conference on Computing Frontiers, 2019
NeuPow: artificial neural networks for power and behavioral modeling of arithmetic components in 45nm ASICs technology.
Proceedings of the 16th ACM International Conference on Computing Frontiers, 2019
2018
NEURAghe: Exploiting CPU-FPGA Synergies for Efficient and Flexible CNN Inference Acceleration on Zynq SoCs.
ACM Trans. Reconfigurable Technol. Syst., 2018
Exploiting All Programmable SoCs in Neural Signal Analysis: A Closed-Loop Control for Large-Scale CMOS Multielectrode Arrays.
IEEE Trans. Biomed. Circuits Syst., 2018
Proceedings of the 2018 International Conference on ReConFigurable Computing and FPGAs, 2018
Automatic Recognition of Complete Atrioventricular Activity in Fetal Pulsed-Wave Doppler Signals.
Proceedings of the 40th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2018
Fetal Pulsed-Wave Doppler Atrioventricular Activity Detection by Envelope Extraction and Processing.
Proceedings of the Computing in Cardiology, 2018
Adaptive Filtering for Electromyographic Signal Processing in Scoliosis Indexes Estimation.
Proceedings of the 11th International Joint Conference on Biomedical Engineering Systems and Technologies (BIOSTEC 2018), 2018
Impact of a TV-based Assistive Technology on Older People's Ability to Self-manage Their Own Health.
Proceedings of the 11th International Joint Conference on Biomedical Engineering Systems and Technologies (BIOSTEC 2018), 2018
Objective Human Gustatory Sensitivity Assessment Through a Portable Electronic Device.
Proceedings of the 2018 IEEE Biomedical Circuits and Systems Conference, 2018
2017
A Precision Pseudo Resistor Bias Scheme for the Design of Very Large Time Constant Filters.
IEEE Trans. Circuits Syst. II Express Briefs, 2017
J. Syst. Archit., 2017
Hardware design methodology using lightweight dataflow and its integration with low power techniques.
J. Syst. Archit., 2017
Challenging the Best HEVC Fractional Pixel FPGA Interpolators With Reconfigurable and Multifrequency Approximate Computing.
IEEE Embed. Syst. Lett., 2017
A Novel Embedded System for Direct, Programmable Stimulation of the Peripheral Neural System.
Proceedings of the New Generation of CAS, 2017
On-FPGA Real-Time Processing of Biological Signals From High-Density MEAs: a Design Space Exploration.
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, 2017
Feasibility Study of Real-Time Spiking Neural Network Simulations on a Swarm Intelligence Based Digital Architecture.
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, 2017
Proceedings of the 2017 39th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), 2017
Comparative evaluation of different wavelet thresholding methods for neural signal processing.
Proceedings of the 2017 39th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
EARNEST: A 64 channel device for neural recording and sensory touch restoration in neural prosthetics.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2017
2016
J. Signal Process. Syst., 2016
J. Signal Process. Syst., 2016
Microprocess. Microsystems, 2016
Microprocess. Microsystems, 2016
Modelling and Automated Implementation of Optimal Power Saving Strategies in Coarse-Grained Reconfigurable Architectures.
J. Electr. Comput. Eng., 2016
Proceedings of the 2016 IEEE International Workshop on Signal Processing Systems, 2016
A high-efficiency runtime reconfigurable IP for CNN acceleration on a mid-range all-programmable SoC.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016
Coarse grain reconfiguration: Power estimation and management flow for hybrid gated systems.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016
Investigation on the hermeticity of an implantable package with 32 feedthroughs for neural prosthetic applications.
Proceedings of the 38th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2016
Proceedings of the 2016 Conference on Design and Architectures for Signal and Image Processing (DASIP), 2016
Low power design methodology for signal processing systems using lightweight dataflow techniques.
Proceedings of the 2016 Conference on Design and Architectures for Signal and Image Processing (DASIP), 2016
The HEREiAM Tele-social-care Platform for Collaborative Management of Independent Living.
Proceedings of the 2016 International Conference on Collaboration Technologies and Systems, 2016
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016
2015
IEEE Trans. Circuits Syst. II Express Briefs, 2015
Computing Swarms for Self-Adaptiveness and Self-Organization in Floating-Point Array Processing.
ACM Trans. Auton. Adapt. Syst., 2015
IET Comput. Digit. Tech., 2015
The challenge of collaborative telerehabilitation: conception and evaluation of a telehealth system enhancement for home-therapy follow-up.
Concurr. Comput. Pract. Exp., 2015
Proceedings of the Symbiotic Interaction - 4th International Workshop, 2015
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015
Home telemonitoring of vital signs through a TV-based application for elderly patients.
Proceedings of the 2015 IEEE International Symposium on Medical Measurements and Applications, 2015
A configurable biopotentials acquisition module suitable for fetal electrocardiography studies.
Proceedings of the 2015 IEEE International Symposium on Medical Measurements and Applications, 2015
Proceedings of the ICT4AgeingWell 2015, 2015
Proceedings of the 2015 Conference on Design and Architectures for Signal and Image Processing, 2015
Proceedings of the 12th ACM International Conference on Computing Frontiers, 2015
2014
Real-time blind audio source separation: performance assessment on an advanced digital signal processor.
J. Supercomput., 2014
J. Real Time Image Process., 2014
A Custom MPSoC Architecture With Integrated Power Management for Real-Time Neural Signal Decoding.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2014
Proceedings of the 2014 IEEE Workshop on Signal Processing Systems, 2014
Automated design flow for coarse-grained reconfigurable platforms: An RVC-CAL multi-standard decoder use-case.
Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014
Online process transformation for polyhedral process networks in shared-memory MPSoCs.
Proceedings of the 3rd Mediterranean Conference on Embedded Computing, 2014
A Stream Buffer Mechanism for Pervasive Splitting Transformations on Polyhedral Process Networks.
Proceedings of the 2nd International Workshop on Many-core Embedded Systems, 2014
Impact of Threshold Computation Methods in Hardware Wavelet Denoising Implementations for Neural Signal Processing.
Proceedings of the Biomedical Engineering Systems and Technologies, 2014
VLSI Wavelet Denoising of Neural Signals - Critical Appraisal of Different Algorithmic Solutions for Threshold Estimation.
Proceedings of the BIODEVICES 2014, 2014
2013
Microprocess. Microsystems, 2013
A system-level approach to adaptivity and fault-tolerance in NoC-based MPSoCs: The MADNESS project.
Microprocess. Microsystems, 2013
Proceedings of the 8th International Symposium on Image and Signal Processing and Analysis, 2013
Proceedings of the 2013 Conference on Design and Architectures for Signal and Image Processing, 2013
A coarse-grained reconfigurable wavelet denoiser exploiting the Multi-Dataflow Composer tool.
Proceedings of the 2013 Conference on Design and Architectures for Signal and Image Processing, 2013
A collaborative approach to the telerehabilitation of patients with hand impairments.
Proceedings of the 2013 International Conference on Collaboration Technologies and Systems, 2013
Identification of Fetal QRS Complexes in Low Density Non-Invasive Biopotential Recordings.
Proceedings of the Computing in Cardiology, 2013
Exploring hardware support for scaling irregular applications on multi-node multi-core architectures.
Proceedings of the 24th International Conference on Application-Specific Systems, 2013
2012
Enabling Fast ASIP Design Space Exploration: An FPGA-Based Runtime Reconfigurable Prototyper.
VLSI Design, 2012
Combining on-hardware prototyping and high-level simulation for DSE of multi-ASIP systems.
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
System Adaptivity and Fault-Tolerance in NoC-based MPSoCs: The MADNESS Project Approach.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing, 2012
Concurrent hybrid switching for massively parallel systems-on-chip: the CYBER architecture.
Proceedings of the Computing Frontiers Conference, CF'12, 2012
An Integrated Portable Device for the Hand Functional Assessment in the Clinical Practice.
Proceedings of the Biomedical Engineering Systems and Technologies, 2012
A Portable Real-time Monitoring System for Kinesitherapic Hand Rehabilitation Exercises.
Proceedings of the BIODEVICES 2012 - Proceedings of the International Conference on Biomedical Electronics and Devices, Vilamoura, Algarve, Portugal, 1, 2012
2011
IEEE Trans. Biomed. Circuits Syst., 2011
Proceedings of the 2011 Conference on Design and Architectures for Signal and Image Processing, 2011
Proceedings of the 2011 International Conference on Collaboration Technologies and Systems, 2011
Towards self-adaptive networks on chip for massively parallel processors: multilevel quality of service programmability.
Proceedings of the 8th Conference on Computing Frontiers, 2011
2010
Proceedings of the Parallel and Distributed Computational Intelligence, 2010
A fast MPI-based parallel framework for cycle-accurate HDL multi-parametric simulations.
Int. J. High Perform. Syst. Archit., 2010
An FPGA-Based Framework for Technology-Aware Prototyping of Multicore Embedded Architectures.
IEEE Embed. Syst. Lett., 2010
Enabling fast Network-on-Chip topology selection: an FPGA-based runtime reconfigurable prototyper.
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010
Proceedings of the NOCS 2010, 2010
Exploiting FPGAs for technology-aware system-level evaluation of multi-core architectures.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2010
Proceedings of the 2010 Conference on Design & Architectures for Signal & Image Processing, 2010
Proceedings of the 7th Conference on Computing Frontiers, 2010
2008
A Novel Non-exclusive Dual-Mode Architecture for MPSoCs-Oriented Network on Chip Designs.
Proceedings of the Embedded Computer Systems: Architectures, 2008
Proceedings of the 2nd International ICST Conference on Pervasive Computing Technologies for Healthcare, 2008
A Network on Chip Architecture for Heterogeneous Traffic Support with Non-Exclusive Dual-Mode Switching.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008
Non-Invasive Real-Time Fetal ECG Extraction - A Block-on-Line DSP Implementation based on the JADE Algorithm.
Proceedings of the First International Conference on Biomedical Electronics and Devices, 2008
A DVB-T Based System for the Diffusion of Tele-Home Care Practice.
Proceedings of the First International Conference on Health Informatics, 2008
2007
A Surface Tension and Coalescence Model for Dynamic Distributed Resources Allocation in Massively Parallel Processors on-Chip.
Proceedings of the Nature Inspired Cooperative Strategies for Optimization (NICSO 2007), 2007
Proceedings of the Nature Inspired Cooperative Strategies for Optimization (NICSO 2007), 2007
VLSI Design, 2007
Synthesis of Predictable Networks-on-Chip-Based Interconnect Architectures for Chip Multiprocessors.
IEEE Trans. Very Large Scale Integr. Syst., 2007
A Layout-Aware Analysis of Networks-on-Chip and Traditional Interconnects for MPSoCs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
Proceedings of the First International Symposium on Networks-on-Chips, 2007
On the impact of serialization on the cache performances in Network-on-Chip based MPSoCs.
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007
2006
J. VLSI Signal Process., 2006
J. Parallel Distributed Comput., 2006
Proceedings of the VLSI-SoC: Research Trends in VLSI and Systems on Chip, 2006
Designing Message-Dependent Deadlock Free Networks on Chips for Application-Specific Systems on Chips.
Proceedings of the IFIP VLSI-SoC 2006, 2006
Proceedings of the 1st International ICST Conference on Nano-Networks, 2006
Proceedings of the 1st International ICST Conference on Nano-Networks, 2006
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006
Automatic Application Partitioning on FPGA/CPU Systems Based on Detailed Low-Level Information.
Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Proceedings of the Ant Colony Optimization and Swarm Intelligence, 2006
2005
A Low-Power Integrated Smart Sensor with on-Chip Real-Time Image Processing Capabilities.
EURASIP J. Adv. Signal Process., 2005
Networks on Chips: A Synthesis Perspective.
Proceedings of the Parallel Computing: Current & Future Issues of High-End Computing, 2005
Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005
Proceedings of the 2005 Design, 2005
2004
Proceedings of the Parallel Problem Solving from Nature, 2004
Proceedings of the Ant Colony Optimization and Swarm Intelligence, 2004
2002
Processing time saving in low power voice coding applications using synchronous reconfigurable co-processing architecture.
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002
2000
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
1999
A modular digital VLSI architecture for stereo depth estimation in industrial applications.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
1998
IEEE Trans. Neural Networks, 1998
Neural Comput. Appl., 1998
Analog computation for phase-based disparity estimation: continuous and discrete models.
Mach. Vis. Appl., 1998
1997
IEEE Trans. Very Large Scale Integr. Syst., 1997
Functional Periodic Intracortical Couplings Induced by Structured Lateral Inhibition in a Linear Cortical Network.
Neural Comput., 1997
Proceedings of the Artificial Neural Networks, 1997
1996
A VLSI Image Processing Architecture Dedicated to Real-Time Quality Control Analysis in an Industrial Plant.
Real Time Imaging, 1996
Neurocomputing, 1996
A programmable VLSI architecture based on multilayer CNN paradigms for real-time visual processing.
Int. J. Circuit Theory Appl., 1996
1995
A neuromorphic architecture for cortical multilayer integration of early visual tasks.
Mach. Vis. Appl., 1995
1993
A neural network architectural model of visual cortical cells for texture segregation.
Proceedings of International Conference on Neural Networks (ICNN'88), San Francisco, CA, USA, March 28, 1993
1990
Proceedings of the European Design Automation Conference, 1990