Carlo Sau

According to our database1, Carlo Sau authored at least 31 papers between 2012 and 2019.

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Bibliography

2019
An integrated hardware/software design methodology for signal processing systems.
J. Syst. Archit., 2019

Dataflow-Functional High-Level Synthesis for Coarse-Grained Reconfigurable Accelerators.
Embedded Systems Letters, 2019

Reconfigurable Adaptive Multiple Transform Hardware Solutions for Versatile Video Coding.
IEEE Access, 2019

Hardware/Software Self-adaptation in CPS: The CERBERO Project Approach.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2019

CERBERO: Cross-layer modEl-based fRamework for multi-oBjective dEsign of reconfigurable systems in unceRtain hybRid envirOnments: Invited paper: CERBERO teams from UniSS, UniCA, IBM Research, TASE, INSA-Rennes, UPM, USI, Abinsula, AmbieSense, TNO, S&T, CRF.
Proceedings of the 16th ACM International Conference on Computing Frontiers, 2019

NeuPow: artificial neural networks for power and behavioral modeling of arithmetic components in 45nm ASICs technology.
Proceedings of the 16th ACM International Conference on Computing Frontiers, 2019

The FitOptiVis ECSEL project: highly efficient distributed embedded image/video processing in cyber-physical systems.
Proceedings of the 16th ACM International Conference on Computing Frontiers, 2019

2018
Multi-Grain Reconfiguration for Advanced Adaptivity in Cyber-Physical Systems.
Proceedings of the 2018 International Conference on ReConFigurable Computing and FPGAs, 2018

2017
Power-Awarness in Coarse-Grained Reconfigurable Multi-Functional Architectures: a Dataflow Based Strategy.
Signal Processing Systems, 2017

Hardware design methodology using lightweight dataflow and its integration with low power techniques.
J. Syst. Archit., 2017

Challenging the Best HEVC Fractional Pixel FPGA Interpolators With Reconfigurable and Multifrequency Approximate Computing.
Embedded Systems Letters, 2017

Feasibility Study of Real-Time Spiking Neural Network Simulations on a Swarm Intelligence Based Digital Architecture.
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, 2017

Challenging CPS Trade-off Adaptivity with Coarse-Grained Reconfiguration.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2017

2016
Automated Design Flow for Multi-Functional Dataflow-Based Platforms.
Signal Processing Systems, 2016

Early Stage Automatic Strategy for Power-Aware Signal Processing Systems Design.
Signal Processing Systems, 2016

Modelling and Automated Implementation of Optimal Power Saving Strategies in Coarse-Grained Reconfigurable Architectures.
J. Electrical and Computer Engineering, 2016

Dataflow-Based Design of Coarse-Grained Reconfigurable Platforms.
Proceedings of the 2016 IEEE International Workshop on Signal Processing Systems, 2016

Demo: Reconfigurable Platform Composer Tool.
Proceedings of the 2016 Conference on Design and Architectures for Signal and Image Processing (DASIP), 2016

Power and clock gating modelling in coarse grained reconfigurable systems.
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016

Adaptable AES implementation with power-gating support.
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016

2015
Computing Swarms for Self-Adaptiveness and Self-Organization in Floating-Point Array Processing.
TAAS, 2015

Coarse-grained reconfiguration: dataflow-based power management.
IET Computers & Digital Techniques, 2015

Reconfigurable coprocessors synthesis in the MPEG-RVC domain.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

Power modelling for saving strategies in coarse grained reconfigurable systems.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

Automated power gating methodology for dataflow-based reconfigurable systems.
Proceedings of the 12th ACM International Conference on Computing Frontiers, 2015

2014
Power-awarness in coarse-grained reconfigurable designs: A dataflow based strategy.
Proceedings of the 2014 IEEE Workshop on Signal Processing Systems, 2014

Automated design flow for coarse-grained reconfigurable platforms: An RVC-CAL multi-standard decoder use-case.
Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014

Automatic generation of dataflow-based reconfigurable co-processing units.
Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing, 2014

2013
DSE and profiling of multi-context coarse-grained reconfigurable systems.
Proceedings of the 8th International Symposium on Image and Signal Processing and Analysis, 2013

A coarse-grained reconfigurable wavelet denoiser exploiting the Multi-Dataflow Composer tool.
Proceedings of the 2013 Conference on Design and Architectures for Signal and Image Processing, 2013

2012
A nature-inspired adaptive floating-point coprocessing system.
Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing, 2012


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