Fabian Kempf

According to our database1, Fabian Kempf authored at least 22 papers between 2002 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.



In proceedings 
PhD thesis 


On csauthors.net:


Leveraging Mixed-Precision CNN Inference for Increased Robustness and Energy Efficiency.
Proceedings of the 36th IEEE International System-on-Chip Conference, 2023

Automated Replacement of State-Holding Flip-Flops to Enable Non-Volatile Checkpointing.
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2023

Leveraging Adaptive Redundancy in Multi-Core Processors for Realizing Adaptive Fault Tolerance in Mixed-Criticality Systems.
Proceedings of the 12th Mediterranean Conference on Embedded Computing, 2023

A Low-Stall Methodology for an Interleaved Processor State Replication.
Proceedings of the 16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2023

SiFI-AI: A Fast and Flexible RTL Fault Simulation Framework Tailored for AI Models and Accelerators.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

The ZuSE-KI-Mobil AI Accelerator SoC: Overview and a Functional Safety Perspective.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

A Hardware-Centric Approach to Increase and Prune Regular Activation Sparsity in CNNs.
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023

Runtime Adaptive Cache Checkpointing for RISC Multi-Core Processors.
Proceedings of the 35th IEEE International System-on-Chip Conference, 2022

Data Movement Reduction for DNN Accelerators: Enabling Dynamic Quantization Through an eFPGA.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

A holistic hardware-software approach for fault-aware embedded systems.
Proceedings of the 25th Euromicro Conference on Digital System Design, 2022

Towards Reconfigurable Accelerators in HPC: Designing a Multipurpose eFPGA Tile for Heterogeneous SoCs.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

FLECSim-SoC: A Flexible End-to-End Co-Design Simulation Framework for System on Chips.
Proceedings of the 34th IEEE International System-on-Chip Conference, 2021

An Adaptive Lockstep Architecture for Mixed-Criticality Systems.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021

Embedded Image Processing the European Way: A new platform for the future automotive market.
Proceedings of the 6th IEEE World Forum on Internet of Things, 2020

Worst-Case Execution-Time-Aware Parallelization of Model-Based Avionics Applications.
J. Aerosp. Inf. Syst., November, 2019

A Network on Chip Adapter for Real-Time and Safety-Critical Applications.
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019

Dynamic and scalable runtime block-based multicast routing for networks on chips.
Proceedings of the 12th International Workshop on Network on Chip Architectures, 2019

Data Readout Triggering for Phase 2 of the Belle II Particle Detector Experiment Based on Neural Networks.
Proceedings of the 31st IEEE International System-on-Chip Conference, 2018

Collaborative Learning in Virtual Classroom Scenarios.
Proceedings of the Learning in the Synergy of Multiple Disciplines, 2009

Virtuelles Kooperieren mit Kreativitätstools in netzbasierten Gruppensitzungen.
Proceedings of the Mensch & Computer 2003: Interaktion in Bewegung, 2003

Kooperation und Wissenskommunikation in 3D-Multiuser-Lernumgebungen.
Proceedings of the Kommunikation in Verteilten Systemen (KiVS), 2003

Referenzmodell zur integrierten Kommunikationsunterstützung von kooperierenden, örtlich verteilten Akteuren.
PhD thesis, 2002