Sebastian Altmeyer

According to our database1, Sebastian Altmeyer authored at least 65 papers between 2007 and 2020.

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Bibliography

2020
Schedulability Analysis of Global Scheduling for Multicore Systems With Shared Caches.
IEEE Trans. Computers, 2020

Hardware Multiversioning for Fail-Operational Multithreaded Applications.
Proceedings of the 32nd IEEE International Symposium on Computer Architecture and High Performance Computing, 2020

Improving the Accuracy of Cache-Aware Response Time Analysis Using Preemption Partitioning.
Proceedings of the 32nd Euromicro Conference on Real-Time Systems, 2020

Towards Energy-, Time- and Security-Aware Multi-core Coordination.
Proceedings of the Coordination Models and Languages, 2020

Investigating Transactional Memory for High Performance Embedded Systems.
Proceedings of the Architecture of Computing Systems - ARCS 2020, 2020

2019
Front Matter - ECRTS 2019 Artifacts, Table of Contents, Preface, Artifact Evaluation Committee.
Dagstuhl Artifacts Ser., 2019

A Survey of Timing Verification Techniques for Multi-Core Real-Time Systems.
ACM Comput. Surv., 2019

Stack memory requirements of AUTOSAR/OSEK-compliant scheduling policies.
Proceedings of the 25th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2019

2018
Task-set generator for schedulability analysis using the TACLebench benchmark suite.
SIGBED Rev., 2018

A Model-Driven Co-Design Framework for Fusing Control and Scheduling Viewpoints.
Sensors, 2018

On the analysis of random replacement caches using static probabilistic timing methods for multi-path programs.
Real Time Syst., 2018

Response-time analysis for fixed-priority systems with a write-back cache.
Real Time Syst., 2018

An extensible framework for multicore response time analysis.
Real Time Syst., 2018

EMPRESS: an Efficient and Effective Method for PREdictable Stack Sharing.
Proceedings of the 24th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2018

Mixed Criticality Systems with Varying Context Switch Costs.
Proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium, 2018

2017
Fixed priority scheduling with pre-emption thresholds and cache-related pre-emption delays: integrated analysis and evaluation.
Real Time Syst., 2017

Schedulability Analysis of Non-preemptive Real-Time Scheduling for Multicore Processors with Shared Caches.
Proceedings of the 2017 IEEE Real-Time Systems Symposium, 2017

Work-in-Progress: Design-Space Exploration of Multi-Core Processors for Safety-Critical Real-Time Systems.
Proceedings of the 2017 IEEE Real-Time Systems Symposium, 2017

Integrated Analysis of Cache Related Preemption Delays and Cache Persistence Reload Overheads.
Proceedings of the 2017 IEEE Real-Time Systems Symposium, 2017

Schedulability using native non-preemptive groups on an AUTOSAR/OSEK platform with caches.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

EDiFy: An Execution time Distribution Finder.
Proceedings of the 54th Annual Design Automation Conference, 2017

2016
Towards a declarative modeling and execution framework for real-time systems.
SIGBED Rev., 2016

Cache related pre-emption delays in hierarchical scheduling.
Real Time Syst., 2016

On the effectiveness of cache partitioning in hard real-time systems.
Real Time Syst., 2016

Dynamics of ferrofluidic flow in the Taylor-Couette system with a small aspect ratio.
CoRR, 2016

TACLeBench: A Benchmark Collection to Support Worst-Case Execution Time Research.
Proceedings of the 16th International Workshop on Worst-Case Execution Time Analysis, 2016

Response Time Analysis of Synchronous Data Flow Programs on a Many-Core Processor.
Proceedings of the 24th International Conference on Real-Time Networks and Systems, 2016

Analysis of Write-back Caches under Fixed-priority Preemptive and Non-preemptive Scheduling.
Proceedings of the 24th International Conference on Real-Time Networks and Systems, 2016

Poster Abstract: An Optimizing Framework for Real-Time Scheduling.
Proceedings of the 2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), 2016

Demo Abstract: Applications of the CPAL Language to Model, Simulate and Program Cyber-Physical Systems.
Proceedings of the 2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), 2016

A model-based development environment for rapid-prototyping of latency-sensitive automotive control software.
Proceedings of the Sixth International Symposium on Embedded Computing and System Design, 2016

Task-Set Generator for Schedulability Analysis using the TACLeBench benchmark suite.
Proceedings of the Embedded Operating Systems Workshop co-located with the Embedded Systems Week (ESWEEK 2016), 2016

2015
Static probabilistic timing analysis for real-time systems using random replacement caches.
Real Time Syst., 2015

WCET and Mixed-Criticality: What does Confidence in WCET Estimations Depend Upon?.
Proceedings of the 15th International Workshop on Worst-Case Execution Time Analysis, 2015

Static Probabilistic Timing Analysis for Multi-path Programs.
Proceedings of the 2015 IEEE Real-Time Systems Symposium, 2015

WCET analysis in shared resources real-time systems with TDMA buses.
Proceedings of the 23rd International Conference on Real Time Networks and Systems, 2015

A generic and compositional framework for multicore response time analysis.
Proceedings of the 23rd International Conference on Real Time Networks and Systems, 2015

Fast and precise cache performance estimation for out-of-order execution.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
A Comparison between Fixed Priority and EDF Scheduling accounting for Cache Related Pre-emption Delays.
Leibniz Trans. Embed. Syst., 2014

Aca 2.0: Questions and Answers.
CoRR, 2014

Integrating Cache-Related Pre-Emption Delays into Analysis of Fixed Priority Scheduling with Pre-Emption Thresholds.
Proceedings of the IEEE 35th IEEE Real-Time Systems Symposium, 2014

Accounting for Cache Related Pre-emption Delays in Hierarchical Scheduling.
Proceedings of the 22nd International Conference on Real-Time Networks and Systems, 2014

Selfish-LRU: Preemption-aware caching for predictability and performance.
Proceedings of the 20th IEEE Real-Time and Embedded Technology and Applications Symposium, 2014

Academia 2.0: removing the publisher middle-man while retaining impact.
Proceedings of the 1st ACM SIGPLAN Workshop on Reproducible Research Methodologies and New Publication Models in Computer Engineering, 2014

OUTSTANDING PAPER: Evaluation of Cache Partitioning for Hard Real-Time Systems.
Proceedings of the 26th Euromicro Conference on Real-Time Systems, 2014

On the correctness, optimality and precision of Static Probabilistic Timing Analysis.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Analysis of preemptively scheduled hard real-time systems.
PhD thesis, 2013

Integrating cache related pre-emption delay analysis into EDF scheduling.
Proceedings of the 19th IEEE Real-Time and Embedded Technology and Applications Symposium, 2013

Analysis of Probabilistic Cache Related Pre-emption Delays.
Proceedings of the 25th Euromicro Conference on Real-Time Systems, 2013

2012
Improved cache related pre-emption delay aware response time analysis for fixed priority pre-emptive systems.
Real Time Syst., 2012

Investigation of Scratchpad Memory for Preemptive Multitasking.
Proceedings of the 33rd IEEE Real-Time Systems Symposium, 2012

Optimising task layout to increase schedulability via reduced cache related pre-emption delays.
Proceedings of the 20th International Conference on Real-Time and Network Systems, 2012

2011
Cache-related preemption delay via useful cache blocks: Survey and redefinition.
J. Syst. Archit., 2011

Cache Related Pre-emption Delay Aware Response Time Analysis for Fixed Priority Pre-emptive Systems.
Proceedings of the 32nd IEEE Real-Time Systems Symposium, 2011

Precise and efficient parametric path analysis.
Proceedings of the ACM SIGPLAN/SIGBED 2011 conference on Languages, 2011

Symbolic Worst Case Execution Times.
Proceedings of the Theoretical Aspects of Computing - ICTAC 2011 - 8th International Colloquium, Johannesburg, South Africa, August 31, 2011

Precise WCET calculation in highly variant real-time systems.
Proceedings of the Design, Automation and Test in Europe, 2011

2010
Precomputing Memory Locations for Parametric Allocations.
Proceedings of the 10th International Workshop on Worst-Case Execution Time Analysis, 2010

Static Timing Analysis for Hard Real-Time Systems.
Proceedings of the Verification, 2010

Resilience analysis: tightening the CRPD bound for set-associative caches.
Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, 2010

2009
Cache-Related Preemption Delay Computation for Set-Associative Caches - Pitfalls and Solutions.
Proceedings of the 9th Intl. Workshop on Worst-Case Execution Time Analysis, 2009

A New Notion of Useful Cache Block to Improve the Bounds of Cache-Related Preemption Delay.
Proceedings of the 21st Euromicro Conference on Real-Time Systems, 2009

2008
WCET Analysis for Preemptive Scheduling.
Proceedings of the 8th Intl. Workshop on Worst-Case Execution Time (WCET) Analysis, 2008

Parametric Timing Analysis for Complex Architectures.
Proceedings of the Fourteenth IEEE Internationl Conference on Embedded and Real-Time Computing Systems and Applications, 2008

2007
Optimal task placement to improve cache performance.
Proceedings of the 7th ACM & IEEE International conference on Embedded software, 2007


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