Piotr Dudek

CoRR, 2024

Factor Machine: Mixed-signal Architecture for Fine-Grained Graph-Based Computing.

[BibT_eX]

[DOI]

CoRR, 2024

2023

PixelRNN: In-pixel Recurrent Neural Networks for End-to-end-optimized Perception with Neural Sensors.

[BibT_eX]

[DOI]

CoRR, 2023

Live Demonstration: SCAMP-7.

[BibT_eX]

[DOI]

Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2023

2022

Sensor-level computer vision with pixel processor arrays for agile robots.

[BibT_eX]

[DOI]

Sci. Robotics, 2022

Pixel Processor Arrays For Low Latency Gaze Estimation.

[BibT_eX]

[DOI]

Proceedings of the 2022 IEEE Conference on Virtual Reality and 3D User Interfaces Abstracts and Workshops, 2022

MantissaCam: Learning Snapshot High-dynamic-range Imaging with Perceptually-based In-pixel Irradiance Encoding.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Computational Photography, 2022

2021

Agile reactive navigation for a non-holonomic mobile robot using a pixel processor array.

[BibT_eX]

[DOI]

IET Image Process., 2021

Direct Servo Control from In-Sensor CNN Inference with A Pixel Processor Array.

[BibT_eX]

[DOI]

CoRR, 2021

Bringing A Robot Simulator to the SCAMP Vision System.

[BibT_eX]

[DOI]

CoRR, 2021

2020

Neural Sensors: Learning Pixel Exposures for HDR Imaging and Video Compressive Sensing With Programmable Sensors.

[BibT_eX]

[DOI]

IEEE Trans. Pattern Anal. Mach. Intell., 2020

Visual Odometry Using Pixel Processor Arrays for Unmanned Aerial Systems in GPS Denied Environments.

[BibT_eX]

[DOI]

Alexander McConville

Robert Clarke

Frontiers Robotics AI, 2020

A Mixed-Signal Spatio-Temporal Signal Classifier for On-Sensor Spike Sorting.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Lessons Learned the Hard Way.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Live Demonstration: CNN Inference on the Focal Plane with a Pixel Processor Array.

[BibT_eX]

[DOI]

Thomas S. Richardson

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Proximity Estimation Using Vision Features Computed On Sensor.

[BibT_eX]

[DOI]

Proceedings of the 2020 IEEE International Conference on Robotics and Automation, 2020

Fully Embedding Fast Convolutional Networks on Pixel Processor Arrays.

[BibT_eX]

[DOI]

Proceedings of the Computer Vision - ECCV 2020, 2020

High-speed Light-weight CNN Inference via Strided Convolutions on a Pixel Processor Array.

[BibT_eX]

[DOI]

Proceedings of the 31st British Machine Vision Conference 2020, 2020

2019

A Camera That CNNs: Towards Embedded Neural Networks on Pixel Processor Arrays.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE/CVF International Conference on Computer Vision, 2019

Live Demonstration: Digit Recognition on Pixel Processor Arrays.

[BibT_eX]

[DOI]

Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition Workshops, 2019

2018

Real-Time Depth From Focus on a Programmable Focal Plane Processor.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Perspective Correcting Visual Odometry for Agile MAVs using a Pixel Processor Array.

[BibT_eX]

[DOI]

Colin Greatwood

Thomas Richardson

Proceedings of the 2018 IEEE/RSJ International Conference on Intelligent Robots and Systems, 2018

Scamp5d Vision System and Development Framework.

[BibT_eX]

[DOI]

Proceedings of the 12th International Conference on Distributed Smart Cameras, 2018

2017

Live demonstration: Depth from focus on a focal plane processor using a focus tunable liquid lens.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

High-speed depth from focus on a programmable vision chip using a focus tunable lens.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Tracking control of a UAV with a parallel visual processor.

[BibT_eX]

[DOI]

Colin Greatwood

Thomas S. Richardson

Proceedings of the 2017 IEEE/RSJ International Conference on Intelligent Robots and Systems, 2017

Visual Odometry for Pixel Processor Arrays.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Computer Vision, 2017

2016

Parallel HDR tone mapping and auto-focus on a cellular processor array vision chip.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

A Demonstration of Tracking using Dynamic Neural Fields on a Programmable Vision Chip: Demo.

[BibT_eX]

[DOI]

Julien N. P. Martel

Yulia Sandamirskaya

Proceedings of the 10th International Conference on Distributed Smart Camera, 2016

2015

Trigger-Wave Asynchronous Cellular Logic Array for Fast Binary Image Processing.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2015

An event-driven massively parallel fine-grained processor array.

[BibT_eX]

[DOI]

Declan Walsh

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Toward joint approximate inference of visual quantities on cellular processor arrays.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Gradient-descent-based learning in memristive crossbar arrays.

[BibT_eX]

[DOI]

Manu V. Nair

Proceedings of the 2015 International Joint Conference on Neural Networks, 2015

Pixel interlacing to trade off the resolution of a cellular processor array against more registers.

[BibT_eX]

[DOI]

Proceedings of the European Conference on Circuit Theory and Design, 2015

2014

Tunable CMOS Delay Gate With Improved Matching Properties.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2014

The accuracy and scalability of continuous-time Bayesian inference in analogue CMOS circuits.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Characterization of processing errors on analog fully-programmable cellular sensor-processor arrays.

[BibT_eX]

[DOI]

Ákos Zarándy

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Live demonstration: A sensor-processor array integrated circuit for high-speed real-time machine vision.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A Fast Self-Tuning Background Subtraction Algorithm.

[BibT_eX]

[DOI]

Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition, 2014

2013

Low power high-performance smart camera system based on SCAMP vision sensor.

[BibT_eX]

[DOI]

J. Syst. Archit., 2013

A Smart Surface Simulation Environment.

[BibT_eX]

[DOI]

Declan Walsh

Proceedings of the IEEE International Conference on Systems, 2013

Metachronal Waves in Cellular Automata: Cilia-Like Manipulation in Actuator Arrays.

[BibT_eX]

[DOI]

Ioannis Georgilas

Andrew Adamatzky

Chris Melhuish

Proceedings of the Nature Inspired Cooperative Strategies for Optimization (NICSO 2013), 2013

Tunable CMOS delay gate with reduced impact of fabrication mismatch on timing parameters.

[BibT_eX]

[DOI]

Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

AMBER: Adapting multi-resolution background extractor.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Image Processing, 2013

Trigger-wave propagation in arbitrary metrics in asynchronous cellular logic arrays.

[BibT_eX]

[DOI]

Proceedings of the 21st European Conference on Circuit Theory and Design, 2013

A general-purpose vision processor with 160×80 pixel-parallel SIMD processor array.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012

Heterogeneous neurons and plastic synapses in a reconfigurable cortical neural network IC.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Trigger-wave collision detecting asynchronous cellular logic array for fast image skeletonization.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Mixed signal SIMD cellular processor array vision chip operating at 30, 000 fps.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

Development of robot self-identification based on visuomotor prediction.

[BibT_eX]

[DOI]

Tao Zhou

Bertram E. Shi

Proceedings of the 2012 IEEE International Conference on Development and Learning and Epigenetic Robotics, 2012

A field programmable array core for image processing (abstract only).

[BibT_eX]

[DOI]

Declan Walsh

Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012

2011

A SIMD Cellular Processor Array Vision Chip With Asynchronous Processing Capabilities.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2011

Asynchronous cellular logic network as a co-processor for a general-purpose massively parallel array.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., 2011

Architecture and design of a programmable 3D-integrated cellular processor array for image processing.

[BibT_eX]

[DOI]

Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

Analogue CMOS circuit implementation of a dopamine modulated synapse.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Live demonstration: Real-time image processing on ASPA2 vision system.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

A processor element for a mixed signal cellular processor array vision chip.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Confession session: Learning from others mistakes.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Self-Organizing Neural Population Coding for improving robotic visuomotor coordination.

[BibT_eX]

[DOI]

Tao Zhou

Bertram E. Shi

Proceedings of the 2011 International Joint Conference on Neural Networks, 2011

Demonstration of a low power image processing system using a SCAMP3 vision chip.

[BibT_eX]

[DOI]

Proceedings of the 2011 Fifth ACM/IEEE International Conference on Distributed Smart Cameras, 2011

2010

An 80×80 general-purpose digital vision chip in 0.18μm CMOS technology.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Using Reinforcement Learning to Guide the Development of Self-organised Feature Maps for Visual Orienting.

[BibT_eX]

[DOI]

Kevin Brohan

Kevin N. Gurney

Proceedings of the Artificial Neural Networks, 2010

2009

Hardware Implementation of Skeletonization Algorithm for Parallel Asynchronous Image Processing.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2009

APRON: A Cellular Processor Array Simulation and Hardware Design Tool.

[BibT_eX]

[DOI]

EURASIP J. Adv. Signal Process., 2009

A pixel-parallel cellular processor array in a stacked three-layer 3D silicon-on-insulator technology.

[BibT_eX]

[DOI]

Viktor Gruev

Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

2008

Compact silicon neuron circuit with spiking and bursting behaviour.

[BibT_eX]

[DOI]

Neural Networks, 2008

Fast retinal vessel tree extraction: A pixel parallel approach.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., 2008

Integrated circuit implementation of a cortical neuron.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Focal-plane moving object segmentation for realtime video surveillance.

[BibT_eX]

[DOI]

David López Vilariño

Diego Cabello

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

ASPA: Focal Plane digital processor array with asynchronous processing capabilities.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Reconfigurable platforms and the challenges for large-scale implementations of spiking neural networks.

[BibT_eX]

[DOI]

Proceedings of the FPL 2008, 2008

Cellular automata and non-static image processing for embodied robot systems on a massively parallel processor array.

[BibT_eX]

Martin Hülse

Proceedings of the Automata 2008: Theory and Applications of Cellular Automata, 2008

2007

Evolution of Pixel Level Snakes towards an efficient hardware implementation.

[BibT_eX]

[DOI]

David López Vilariño

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Spiking and Bursting Firing Patterns of a Compact VLSI Cortical Neuron Circuit.

[BibT_eX]

[DOI]

Proceedings of the International Joint Conference on Neural Networks, 2007

Implementation of multi-layer leaky integrator networks on a cellular processor array.

[BibT_eX]

[DOI]

Jonathan M. Chambers

Kevin N. Gurney

Proceedings of the International Joint Conference on Neural Networks, 2007

Implementation of an asynchronous cellular logic network as a co-processor for a general-purpose massively parallel array.

[BibT_eX]

[DOI]

Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

On chip implementation of a pixel-parallel approach for retinal vessel tree extraction.

[BibT_eX]

[DOI]

Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

2006

An asynchronous cellular logic network for trigger-wave image processing on fine-grain massively parallel arrays.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2006

Architecture of a VLSI cellular processor array for synchronous/asynchronous image processing.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Simple Analogue VLSI Circuit of a Cortical Neuron.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on Electronics, 2006

2005

A general-purpose processor-per-pixel analog SIMD vision chip.

[BibT_eX]

[DOI]

Peter J. Hicks

IEEE Trans. Circuits Syst. I Regul. Pap., 2005

Implementation of SIMD vision chip with 128×128 array of analogue processing elements.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Architecture of asynchronous cellular processor array for image skeletonization.

[BibT_eX]

[DOI]

Aliaksei Lopich

Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005

An area and power efficient discrete-time chaos generator circuit.

[BibT_eX]

[DOI]

V. D. Juncu

Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005

2004

A 39×48 general-purpose focal-plane processor array integrated circuit.

[BibT_eX]

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003

A flexible global readout architecture for an analogue SIMD vision chip.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2001

An analogue SIMD focal-plane processor array.

[BibT_eX]

[DOI]

Peter J. Hicks

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

2000

A high-resolution CMOS time-to-digital converter utilizing a Vernier delay line.

[BibT_eX]

[DOI]

Stanislaw Szczepanski

John V. Hatfield

IEEE J. Solid State Circuits, 2000

A CMOS general-purpose sampled-data analogue microprocessor.

[BibT_eX]

[DOI]