Gerrit den Besten

According to our database, Gerrit den Besten authored at least 14 papers between 1998 and 2019.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of four.

2019

Single-Pair Automotive PHY Solutions from 10Mb/s to 10Gb/s and Beyond.

Gerrit W. den Besten

Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2016

F4: Emerging short-reach and high-density interconnect solutions for internet of everything.

Ichiro Fujimori, Martin Brox, Elad Alon, Pavan Kumar Hanumolu, Gerrit den Besten, Hideyuki Nosaka

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015

Session 10 overview: Advanced wireline techniques and PLLs: Wireline subcommittee.

Gerrit den Besten, Ajith Amerasekera

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2013

Session 23 overview: Short-reach links, XCVR techniques, & PLLs.

Gerrit den Besten, Koichi Yamaguchi

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

F3: Emerging technologies for wireline communication.

Elad Alon, Azita Emami, Gerrit den Besten, Ichiro Fujimori, Tadahiro Kuroda, Masafumi Nogawa, Hisakatsu Yamaguchi

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

Current-steering pre-emphasis transmitter with continuously tuned line terminations for optimum impedance match and maximum signal drive range.

Gerrit den Besten, Harold G. Hanson, Ranjeet K. Gupta

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012

A 1.2-6 Gb/s, 4.2 pJ/Bit Clock & Data Recovery Circuit With High Jitter Tolerance in 0.14 µm CMOS.

Arnoud P. van der Wel, Gerrit den Besten

IEEE J. Solid State Circuits, 2012

High-speed wireline transceivers and clocking.

Gerrit den Besten, Shunichi Kaeriyama

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2011

A 1.2-6 Gb/s, 4.2 pJ/bit Clock & Data Recovery circuit with high jitter tolerance in 0.14μm CMOS.

Arnoud P. van der Wel, Gerrit den Besten

Proceedings of the 37th European Solid-State Circuits Conference, 2011

2009

A Robust High Speed Serial PHY Architecture With Feed-Forward Correction Clock and Data Recovery.

William Redman-White, Martin Bugbee, Steve Dobbs, Xinyan Wu, Richard A. H. Balmford, Jonah Nuttgens, Umer Salim Kiani, Richard Clegg, Gerrit W. den Besten

IEEE J. Solid State Circuits, 2009

2008

A 0.2-2 Gb/s 6x OSR Receiver Using a Digitally Self-Adaptive Equalizer.

Friedel Gerfers, Gerrit W. den Besten, Pavel V. Petkov, Jim E. Conder, Andreas J. Koellmann

IEEE J. Solid State Circuits, 2008

A robust 1.5Gb/s + 3Gb/s serial PHY with feed-forward correction clock and data recovery.

William Redman-White, Martin Bugbee, Steve Dobbs, Xinyan Wu, Richard A. H. Balmford, Jonah Nuttgens, Umer Salim Kiani, Richard Clegg, Gerrit W. den Besten

Proceedings of the ESSCIRC 2008, 2008

2000

Applying Asynchronous Circuits in Contactless Smart Cards.

Joep L. W. Kessels, Gerrit den Besten, Ad M. G. Peeters, Torsten Kramer, Volker Timm

Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000), 2000

1998

Embedded 5 V-to-3.3 V voltage regulator for supplying digital IC's in 3.3 V CMOS technology.

Gerrit W. den Besten, Bram Nauta

IEEE J. Solid State Circuits, 1998