Gjalt G. de Jong

According to our database1, Gjalt G. de Jong authored at least 25 papers between 1991 and 2008.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2008
An Industrial Case: Pitfalls and Benefits of Applying Formal Methods to the Development of a Network-Centric RTOS.
Proceedings of the FM 2008: Formal Methods, 2008

2007
OpenComRTOS: An Ultra-Small Network Centric Embedded RTOS Designed Using Formal Modeling.
Proceedings of the SDL 2007: Design for Dependable Systems, 2007

2002
A UML-Based Design Methodology for Real-Time and Embedded Systems.
Proceedings of the 2002 Design, 2002

2001
C/C++: progress or deadlock in system-level specification.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

2000
An Incremental Specification Flow for Real Time Embedded Systems.
Proceedings of the 2000 Design, 2000

Standards for System-Level Design: Practical Reality or Solution in Search of a Question?
Proceedings of the 2000 Design, 2000

1999
Matisse: A System-on-Chip Design Methodology Emphasizing Dynamic Memory Management.
J. VLSI Signal Process., 1999

Minimizing the required memory bandwidth in VLSI system realizations.
IEEE Trans. Very Large Scale Integr. Syst., 1999

Memory management for embedded network applications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

How standards will enable hardware/software co-design.
Proceedings of the Seventh International Workshop on Hardware/Software Codesign, 1999

1998
Efficient Verification using Generalized Partial Order Analysis.
Proceedings of the 1998 Design, 1998

Efficient System Exploration and Synthesis of Applications with Dynamic Data Storage and Intensive Data Transfer.
Proceedings of the 35th Conference on Design Automation, 1998

1997
Derivation of Formal Representations from Process-Based Specification and Implementation Models.
Proceedings of the 10th International Symposium on System Synthesis, 1997

Fast and Extensive System-Level Memory Exploration for ATM Applications.
Proceedings of the 10th International Symposium on System Synthesis, 1997

A System Design Methodology for Telecommunication Network Applications.
Proceedings of the 7th Great Lakes Symposium on VLSI (GLS-VLSI '97), 1997

Multi-thread graph: a system model for real-time embedded software synthesis.
Proceedings of the European Design and Test Conference, 1997

1996
Flow Graph Balancing for Minimizing the Required Memory Bandwidth.
Proceedings of the 9th International Symposium on System Synthesis, 1996

Efficient Partial Enumeration for Timing Analysis of Asynchronous Systems.
Proceedings of the 33st Conference on Design Automation, 1996

1995
Background memory management for dynamic data structure intensive processing systems.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Modeling and optimization of hierarchical synchronous circuits.
Proceedings of the 1995 European Design and Test Conference, 1995

Hierarchical Optimization of Asynchronous Circuits.
Proceedings of the 32st Conference on Design Automation, 1995

1994
A Time Abstraction Method for Efficient Verification of Communicating Systems.
Proceedings of the 31st Conference on Design Automation, 1994

A Communicating Petri Net Model for the Design of Concurrent Asynchronous Modules.
Proceedings of the 31st Conference on Design Automation, 1994

1991
Data flow graphs: system specification with the most unrestricted semantics.
Proceedings of the conference on European design automation, 1991

An Automata Theoretic Approach to Temporal Logic.
Proceedings of the Computer Aided Verification, 3rd International Workshop, 1991


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