Diederik Verkest

According to our database1, Diederik Verkest authored at least 139 papers between 1989 and 2022.

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Bibliography

2022
AERO: Design Space Exploration Framework for Resource-Constrained CNN Mapping on Tile-Based Accelerators.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022

DIANA: An End-to-End Energy-Efficient Digital and ANAlog Hybrid Neural Network SoC.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022

2021
Charge Sharing and Charge Injection A/D Converters for Analog In-Memory Computing.
Proceedings of the 19th IEEE International New Circuits and Systems Conference, 2021

Design-Technology Space Exploration for Energy Efficient AiMC-Based Inference Acceleration.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Noise tolerant ternary weight deep neural networks for analog in-memory inference.
Proceedings of the International Joint Conference on Neural Networks, 2021

A 22 nm, 1540 TOP/s/W, 12.1 TOP/s/mm<sup>2</sup> in-Memory Analog Matrix-Vector-Multiplier for DNN Acceleration.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021

2019
FQ-Conv: Fully Quantized Convolution for Efficient and Accurate Inference.
CoRR, 2019

Low Voltage Transient RESET Kinetic Modeling of OxRRAM for Neuromorphic Applications.
Proceedings of the IEEE International Reliability Physics Symposium, 2019

2018
Scaling CMOS beyond Si FinFET: an analog/RF perspective.
Proceedings of the 48th European Solid-State Device Research Conference, 2018

2017
Statistical Timing Analysis Considering Device and Interconnect Variability for BEOL Requirements in the 5-nm Node and Beyond.
IEEE Trans. Very Large Scale Integr. Syst., 2017

SRAM designs for 5nm node and beyond: Opportunities and challenges.
Proceedings of the 2017 IEEE International Conference on IC Design and Technology, 2017

2016
5nm: Has the time for a device change come?
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

Physical Design Solutions to Tackle FEOL/BEOL Degradation in Gate-level Monolithic 3D ICs.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

2015
STT-MRAM cell design with partial source line planes: improving the trade-off between area and series resistance.
Proceedings of the IEEE Non-Volatile Memory System and Applications Symposium, 2015

Lateral NWFET optimization for beyond 7nm nodes.
Proceedings of the 2015 International Conference on IC Design & Technology, 2015

Impact of fin shape variability on device performance towards 10nm node.
Proceedings of the 2015 International Conference on IC Design & Technology, 2015

Modeling FinFET metal gate stack resistance for 14nm node and beyond.
Proceedings of the 2015 International Conference on IC Design & Technology, 2015

Impact of device and interconnect process variability on clock distribution.
Proceedings of the 2015 International Conference on IC Design & Technology, 2015

Dimensioning for power and performance under 10nm: The limits of FinFETs scaling.
Proceedings of the 2015 International Conference on IC Design & Technology, 2015

Design technology co-optimization for enabling 5nm gate-all-around nanowire 6T SRAM.
Proceedings of the 2015 International Conference on IC Design & Technology, 2015

Impact of interconnect multiple-patterning variability on SRAMs.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Characterization and simulation methodology for time-dependent variability in advanced technologies.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

Holisitic device exploration for 7nm node.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

A digital intensive circuit for low-frequency noise monitoring in 28nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

2014
System-level assessment and area evaluation of Spin Wave logic circuits.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2014

Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies.
Proceedings of the 44th European Solid State Device Research Conference, 2014


2013
TEASE: a systematic analysis framework for early evaluation of FinFET-based advanced technology nodes.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Design issues in heterogeneous 3D/2.5D integration.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
Trades-off between lithography line edge roughness and error-correcting codes requirements for NAND Flash memories.
Microelectron. Reliab., 2012

2011
Real-time high-definition stereo matching on FPGA.
Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

Analysis of microbump induced stress effects in 3D stacked IC technologies.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

2010
A Safari Through the MPSoC Run-Time Management Jungle.
J. Signal Process. Syst., 2010

Modeling and exploiting spatial locality trade-offs in wavelet-based applications under varying resource requirements.
ACM Trans. Embed. Comput. Syst., 2010

Circuit Design for Bias Compatibility in Novel FinFET-Based Floating-Body RAM.
IEEE Trans. Circuits Syst. II Express Briefs, 2010

2009
Design and Tool Flow of Multimedia MPSoC Platforms.
J. Signal Process. Syst., 2009

Power Dissipation of the Network-on-Chip in Multi-Processor System-on-Chip Dedicated for Video Coding Applications.
J. Signal Process. Syst., 2009

Exploiting Varying Resource Requirements in Wavelet-based Applications in Dynamic Execution Environments.
J. Signal Process. Syst., 2009

Interconnect Exploration for Energy Versus Performance Tradeoffs for Coarse Grained Reconfigurable Architectures.
IEEE Trans. Very Large Scale Integr. Syst., 2009

Spatial locality exploitation for runtime reordering of JPEG2000 wavelet data layouts.
ACM Trans. Design Autom. Electr. Syst., 2009

Distributed Loop Controller for Multithreading in Unithreaded ILP Architectures.
IEEE Trans. Computers, 2009

3-D Technology Assessment: Path-Finding the Technology/Design Sweet-Spot.
Proc. IEEE, 2009

EMPIRE: Empirical power/area/timing models for register files.
Microprocess. Microsystems, 2009

Multimedia systems in a changing technology landscape.
Proceedings of the 7th IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia, 2009

2008
Run-Time Management of a MPSoC Containing FPGA Fabric Tiles.
IEEE Trans. Very Large Scale Integr. Syst., 2008

Concepts and Implementation of Spatial Division Multiplexing for Guaranteed Throughput in Networks-on-Chip.
IEEE Trans. Computers, 2008

A Coarse-Grained Array Accelerator for Software-Defined Radio Baseband Processing.
IEEE Micro, 2008

Joint hardware-software leakage minimization approach for the register file of VLIW embedded architectures.
Integr., 2008

Energy-Aware Interconnect Optimization for a Coarse Grained Reconfigurable Processor.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Interconnect Power Analysis for a Coarse-Grained Reconfigurable Array Processor.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008

Spatial locality trade-offs of wavelet-based applications in dynamic execution environments.
Proceedings of the IEEE International Conference on Acoustics, 2008

Coffee: COmpiler Framework for Energy-Aware Exploration.
Proceedings of the High Performance Embedded Architectures and Compilers, 2008

2007
Energy-aware compilation and hardware design for VLIW embedded systems.
Int. J. Embed. Syst., 2007

A Systematic Approach to Design Low-Power Video Codec Cores.
EURASIP J. Embed. Syst., 2007

Exploiting the Expressiveness of Cyclo-Static Dataflow to Model Multimedia Implementations.
EURASIP J. Adv. Signal Process., 2007

Semi Custom Design: A Case Study on SIMD Shufflers.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007

A Quick Safari Through the MPSoC Run-Time Management Jungle.
Proceedings of the 2007 5th Workshop on Embedded Systems for Real-Time Multimedia, 2007

Adaptive mapping to resource availability for dynamic wavelet-based applications.
Proceedings of the 2007 5th Workshop on Embedded Systems for Real-Time Multimedia, 2007

Very wide register: an asymmetric register file organization for low power embedded processors.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

A Customized Cross-Bar for Data-Shuffling in Domain-Specific SIMD Processors.
Proceedings of the Architecture of Computing Systems, 2007

2006
Software-Controlled Scratchpad Mapping Strategies for Wavelet-Based Applications.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2006

Software Simultaneous Multi-Threading, a Technique to Exploit Task-Level Parallelism to Improve Instruction- and Data-Level Parallelism.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

Compiler-Driven Leakage Energy Reduction in Banked Register Files.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

Exploiting Hierarchical Configuration to Improve Run-Time MPSoC Task Assignment.
Proceedings of the 2006 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2006

Distributed loop controller architecture for multi-threading in uni-threaded VLIW processors.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005
A Reconfiguration Manager for Dynamically Reconfigurable Hardware.
IEEE Des. Test Comput., 2005

Architecture Exploration for a Reconfigurable Architecture Template.
IEEE Des. Test Comput., 2005

Memory Hierarchy Energy Cost of a Direct Filtering Implementation of the Wavelet Transform.
Proceedings of the Integrated Circuit and System Design, 2005

Object-Distribution Analysis for Program Decomposition and Re-Clustering.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

Object-Distribution Analysis: Technique for Parallel Loop Distribution of Object-Oriented Programs.
Proceedings of the 34th International Conference on Parallel Processing Workshops (ICPP 2005 Workshops), 2005

Centralized end-to-end flow control in a best-effort network-on-chip.
Proceedings of the EMSOFT 2005, 2005

Low Cost Task Migration Initiation in a Heterogeneous MP-SoC.
Proceedings of the 2005 Design, 2005

Spatial division multiplexing: a novel approach for guaranteed throughput on NoCs.
Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005

Power Breakdown Analysis for a Heterogeneous NoC Platform Running a Video Application.
Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005

2004
A hybrid design-time/run-time scheduling flow to minimise the reconfiguration overhead of FPGAs.
Microprocess. Microsystems, 2004

Run-time support for heterogeneous multitasking on reconfigurable SoCs.
Integr., 2004

Design Style Case Study for Embedded Multi Media Compute Nodes.
Proceedings of the 25th IEEE Real-Time Systems Symposium (RTSS 2004), 2004

High-Level Data-Access Analysis for Characterisation of (Sub)task-Level Parallelism in Java.
Proceedings of the 9th International Workshop on High-Level Programming Models and Supportive Environments (HIPS 2004), 2004

Network-on-Chip for Reconfigurable Systems: From High-Level Design Down to Implementation.
Proceedings of the Field Programmable Logic and Application, 2004

Design-Time Data-Access Analysis for Parallel Java Programs with Shared-Memory Communication Model.
Proceedings of the Euro-Par 2004 Parallel Processing, 2004

Design Methodology for a Tightly Coupled VLIW/Reconfigurable Matrix Architecture: A Case Study.
Proceedings of the 2004 Design, 2004

Operating-system controlled network on chip.
Proceedings of the 41th Design Automation Conference, 2004

2003
Power-efficient flexible processor architecture for embedded applications.
IEEE Trans. Very Large Scale Integr. Syst., 2003

Hardware Architectures for the Efficient Implementation of Multi-Service Broadband Access and Multimedia Home Networks.
Telecommun. Syst., 2003

Performance Analysis for Identification of (Sub-)Task-Level Parallelism in Java.
Proceedings of the Software and Compilers for Embedded Systems, 7th International Workshop, 2003

Highly scalable network on chip for reconfigurable systems.
Proceedings of the 2003 International Symposium on System-on-Chip, 2003

Designing an Operating System for a Heterogeneous Reconfigurable So.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003

Run-Time Minimization of Reconfiguration Overhead in Dynamically Reconfigurable Systems.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

Networks on Chip as Hardware Components of an OS for Reconfigurable Systems.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

Application of Task Concurrency Management on Dynamically Reconfigurable Hardware Platforms.
Proceedings of the 11th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2003), 2003

Run-Time Scheduling for Multimedia Applications on Dynamically Reconfigurable Systems.
Proceedings of the First Workshop on Embedded Systems for Real-Time Multimedia, 2003

Hierarchical Run-Time Reconfiguration Managed by an Operating System for Reconfigurable Systems.
Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, June 23, 2003

Infrastructure for Design and Management of Relocatable Tasks in a Heterogeneous Reconfigurable System-on-Chip.
Proceedings of the 2003 Design, 2003

Exploiting Loop-Level Parallelism on Coarse-Grained Reconfigurable Architectures Using Modulo Scheduling.
Proceedings of the 2003 Design, 2003

2002
Dynamic memory management methodology applied to embedded telecom network systems.
IEEE Trans. Very Large Scale Integr. Syst., 2002

Design of Cam-E-leon, a Run-Time Reconfigurable Web Camera.
Proceedings of the Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation, 2002

DRESC: a retargetable compiler for coarse-grained reconfigurable architectures.
Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, 2002

Interconnection Networks Enable Fine-Grain Dynamic Multi-tasking on FPGAs.
Proceedings of the Field-Programmable Logic and Applications, 2002

Adding Hardware Support to the HotSpot Virtual Machine for Domain Specific Applications.
Proceedings of the Field-Programmable Logic and Applications, 2002

Design Technology for Networked Reconfigurable FPGA Platforms.
Proceedings of the 2002 Design, 2002

System-level performance optimization of the data queueing memory management in high-speed network processors.
Proceedings of the 39th Design Automation Conference, 2002

2001
Energy-Aware Runtime Scheduling for Embedded-Multiprocessor SOCs.
IEEE Des. Test Comput., 2001

Systematic speed-power memory data-layout exploration for cache controlled embedded multimedia applications.
Proceedings of the 14th International Symposium on Systems Synthesis, 2001

System-level interconnect architecture exploration for custom memory organizations.
Proceedings of the 14th International Symposium on Systems Synthesis, 2001

Optimisation Problems for Dynamic Concurrent Task-Based Systems.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

Task concurrency management methodology summary.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

2000
Formalized three-layer system-level model and reuse methodology for embedded data-dominated applications.
IEEE Trans. Very Large Scale Integr. Syst., 2000

Dynamic Memory Oriented Transformations in the MPEG4 IM1-Player on a Low Power Platform.
Proceedings of the Power-Aware Computer Systems, First International Workshop, 2000

Flexible hardware acceleration for multimedia oriented microprocessors.
Proceedings of the 33rd Annual IEEE/ACM International Symposium on Microarchitecture, 2000

Task Concurrency Management Experiment for Power-Efficient Speed-up of Embedded MPEG4 IM1 Player.
Proceedings of the 2000 International Workshop on Parallel Processing, 2000

Formalized Three-Layer System-Level Reuse Model and Methodology for Embedded Data-Dominated Applications.
Proceedings of the 2000 Design, 2000

System Level Design Using C++.
Proceedings of the 2000 Design, 2000

Operating system based software generation for systems-on-chip.
Proceedings of the 37th Conference on Design Automation, 2000

Extended design reuse trade-offs in hardware-software architecture mapping.
Proceedings of the Eighth International Workshop on Hardware/Software Codesign, 2000

Dynamic scheduling of concurrent tasks with cost performance trade-off.
Proceedings of the 2000 International Conference on Compilers, 2000

1999
Matisse: A System-on-Chip Design Methodology Emphasizing Dynamic Memory Management.
J. VLSI Signal Process., 1999

Guest Editorial.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Exploration and Synthesis of Dynamic Data Sets in Telecom Network Applications.
Proceedings of the 12th International Symposium on System Synthesis, 1999

Hardware-software co-design of embedded systems using CoWare's N2C methodology for application development.
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

Combining Software Synthesis and Hardware/Software Interface Generation to Meet Hard Real-Time Constraints.
Proceedings of the 1999 Design, 1999

Global Multimedia System Design Exploration Using Accurate Memory Organization Feedback.
Proceedings of the 36th Conference on Design Automation, 1999

Timed executable system specification of an ADSL modem using a C++ based design environment: a case study.
Proceedings of the Seventh International Workshop on Hardware/Software Codesign, 1999

1998
Proposal for Unified System Design Meta Flow in Task-Level and Instruction-Level Design Technology Research for Multi-Media Applications.
Proceedings of the 11th International Symposium on System Synthesis, 1998

Power exploration for dynamic data types through virtual memory management refinement.
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

Efficient Verification using Generalized Partial Order Analysis.
Proceedings of the 1998 Design, 1998

Efficient System Exploration and Synthesis of Applications with Dynamic Data Storage and Intensive Data Transfer.
Proceedings of the 35th Conference on Design Automation, 1998

1997
Hardware/software co-design of digital telecommunication systems.
Proc. IEEE, 1997

Derivation of Formal Representations from Process-Based Specification and Implementation Models.
Proceedings of the 10th International Symposium on System Synthesis, 1997

1996
CoWare - A design environment for heterogeneous hardware/software systems.
Des. Autom. Embed. Syst., 1996

CoWare - a design environment for heterogenous hardware/software systems.
Proceedings of the conference on European design automation, 1996

1994
A Proof of the Nonrestoring Division Algorithm and its Implementation on an ALU.
Formal Methods Syst. Des., 1994

1993
On the Comparison of HOL and Boyer-Moore for Formal Hardware Verification.
Formal Methods Syst. Des., 1993

1992
A Description Methodology for Parameterized Modules in the Boyer-Moore Logic.
Proceedings of the Theorem Provers in Circuit Design, 1992

A Proof of the Non-Restoring Division Algorithm and its Implementation on the Cathedral-II ALU.
Proceedings of the Designing Correct Circuits, 1992

1991
Formal Hardware Verification in HOL and in Boyer-Moore: A Comparative Analysis.
Proceedings of the 1991 International Workshop on the HOL Theorem Proving System and its Applications, 1991

1990
Correctness proofs of parameterized hardware modules in the CATHEDRAL-II synthesis environment.
Proceedings of the European Design Automation Conference, 1990

1989
Description and verification of more-dimensional regular and non-homogeneous structures using a functional hardware description language.
Microprocessing and Microprogramming, 1989

Application of system semantics to VLSI for the transformational design of a parameterized booth multiplier module - a case study.
Microprocessing and Microprogramming, 1989


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