Ana Sonia Leon

According to our database, Ana Sonia Leon authored at least 10 papers between 2004 and 2026.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2026

10.6 A Hybrid-Bonded 12.1Tops/mm² 5 6-Core DNN Processor with 2.5Tb/s/mm² 3D Network on Chip.

Phil C. Knag, Gregory K. Chen, Shanshan Xie, Satish Yada, Wei Wu, Yu-Shiang Lin, Alexander Kashirin, Xiemei Meng, Russell Criss, Ana Sonia Leon, Carlos Tokunaga, Ram K. Krishnamurthy, James W. Tschanz

Proceedings of the IEEE International Solid-State Circuits Conference, 2026

2011

A 40 nm 16-Core 128-Thread SPARC SoC Processor.

Jinuk Luke Shin, Dawei Huang, Bruce Petrick, Changku Hwang, Kenway W. Tam, Alan P. Smith, Ha Pham, Hongping Penny Li, Timothy Johnson, Francis Schumacher, Ana Sonia Leon, Allan Strong

IEEE J. Solid State Circuits, 2011

2010

A 40nm 16-core 128-thread CMT SPARC SoC processor.

Jinuk Luke Shin, Kenway W. Tam, Dawei Huang, Bruce Petrick, Ha Pham, Changku Hwang, Hongping Penny Li, Alan P. Smith, Timothy Johnson, Francis Schumacher, David Greenhill, Ana Sonia Leon, Allan Strong

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2007

A Power-Efficient High-Throughput 32-Thread SPARC Processor.

Ana Sonia Leon, Kenway W. Tam, Jinuk Luke Shin, David Weisner, Francis Schumacher

IEEE J. Solid State Circuits, 2007

2006

A Power-Efficient High-Throughput 32-Thread SPARC Processor.

Ana Sonia Leon, Jinuk Luke Shin, Kenway W. Tam, William Bryg, Francis Schumacher, Poonacha Kongetira, David Weisner, Allan Strong

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

The UltraSPARC T1 Processor: CMT Reliability.

Ana Sonia Leon, Brian Langley, Jinuk Luke Shin

Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2005

A dual-core 64-bit ultraSPARC microprocessor for dense server applications.

Toshinari Takayanagi, Jinuk Luke Shin, Bruce Petrick, Jeffrey Y. Su, Howard Levy, Ha Pham, Jinseung Son, Nathan Moon, Dina Bistry, Umesh Nair, Mandeep Singh, Vikas Mathur, Ana Sonia Leon

IEEE J. Solid State Circuits, 2005

Design and implementation of an embedded 512-KB level-2 cache subsystem.

Jinuk Luke Shin, Bruce Petrick, Mandeep Singh, Ana Sonia Leon

IEEE J. Solid State Circuits, 2005

2004

A dual-core 64b ultraSPARC microprocessor for dense server applications.

Toshinari Takayanagi, Jinuk Luke Shin, Bruce Petrick, Jeffrey Y. Su, Ana Sonia Leon

Proceedings of the 41th Design Automation Conference, 2004

Design and implementation of an embedded 512KB level 2 cache subsystem.

Jinuk Luke Shin, Bruce Petrick, Howard Levy, Jinseung Son, Mandeep Singh, Vikas Mathur, Jung-Cheng Yeh, Heesung Choi, Vishal Gupta, Tom Ziaja, Ana Sonia Leon

Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004