Hanchen Ye

Orcid: 0000-0002-6646-8146

According to our database1, Hanchen Ye authored at least 13 papers between 2020 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2024
New Solutions on LLM Acceleration, Optimization, and Application.
CoRR, 2024

SnapKV: LLM Knows What You are Looking for Before Generation.
CoRR, 2024

Subgraph Extraction-Based Feedback-Guided Iterative Scheduling for HLS.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

HIDA: A Hierarchical Dataflow Compiler for High-Level Synthesis.
Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2024

2023
AutoScaleDSE: A Scalable Design Space Exploration Engine for High-Level Synthesis.
ACM Trans. Reconfigurable Technol. Syst., September, 2023

High-level Synthesis for Domain Specific Computing.
Proceedings of the 2023 International Symposium on Physical Design, 2023

CHARM: Composing Heterogeneous AcceleRators for Matrix Multiply on Versal ACAP Architecture.
Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2023

2022
ScaleHLS: A New Scalable High-Level Synthesis Framework on Multi-Level Intermediate Representation.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022

ScaleHLS: a scalable high-level synthesis framework with multi-level transformations and optimizations: invited.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021
ScaleHLS: Scalable High-Level Synthesis through MLIR.
CoRR, 2021

Being-ahead: Benchmarking and Exploring Accelerators for Hardware-Efficient AI Deployment.
CoRR, 2021

2020
DNNExplorer: A Framework for Modeling and Exploring a Novel Paradigm of FPGA-based DNN Accelerator.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

HybridDNN: A Framework for High-Performance Hybrid DNN Accelerator Design and Implementation.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020


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