Haoran Li
Orcid: 0000-0002-3478-9260Affiliations:
- Alibaba DAMO Academy Computing Technology Laboratory, Hangzhou, China
- Hong Kong University of Science and Technology, Department of Electronic and Computer Engineering, Hong Kong (PhD 2019)
According to our database1,
Haoran Li
authored at least 20 papers
between 2015 and 2020.
Collaborative distances:
Collaborative distances:
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Bibliography
2020
IEEE Trans. Very Large Scale Integr. Syst., 2020
Chip-Specific Power Delivery and Consumption Co-Management for Process-Variation-Aware Manycore Systems Using Reinforcement Learning.
IEEE Trans. Very Large Scale Integr. Syst., 2020
2019
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
2018
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
Proceedings of the 36th IEEE International Conference on Computer Design, 2018
Co-manage power delivery and consumption for manycore systems using reinforcement learning.
Proceedings of the International Conference on Computer-Aided Design, 2018
Merge-Based Parallel Sparse Matrix-Sparse Vector Multiplication with a Vector Architecture.
Proceedings of the 20th IEEE International Conference on High Performance Computing and Communications; 16th IEEE International Conference on Smart City; 4th IEEE International Conference on Data Science and Systems, 2018
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
2017
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
Adaptive power delivery system management for many-core processors with on/off-chip voltage regulators.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Proceedings of the 54th Annual Design Automation Conference, 2017
Modular reinforcement learning for self-adaptive energy efficiency optimization in multicore system.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
A Holistic Modeling and Analysis of Optical-Electrical Interfaces for Inter/Intra-chip Interconnects.
IEEE Trans. Very Large Scale Integr. Syst., 2016
An Adaptive Process-Variation-Aware Technique for Power-Gating-Induced Power/Ground Noise Mitigation in MPSoC.
IEEE Trans. Very Large Scale Integr. Syst., 2016
Coherent and Incoherent Crosstalk Noise Analyses in Interchip/Intrachip Optical Interconnection Networks.
IEEE Trans. Very Large Scale Integr. Syst., 2016
Alleviate Chip Pin Constraint for Multicore Processor by On/Off-Chip Power Delivery System Codesign.
ACM J. Emerg. Technol. Comput. Syst., 2016
JADE: a Heterogeneous Multiprocessor System Simulation Platform Using Recorded and Statistical Application Models.
Proceedings of the 1st International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems, 2016
2015
Adaptively tolerate power-gating-induced power/ground noise under process variations.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Alleviate chip I/O pin constraints for multicore processors through optical interconnects.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015