Mahdi Nikdast

Orcid: 0000-0003-4930-2985

According to our database1, Mahdi Nikdast authored at least 78 papers between 2010 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

Online presence:

On csauthors.net:

Bibliography

2024
Lightator: An Optical Near-Sensor Accelerator with Compressive Acquisition Enabling Versatile Image Processing.
CoRR, 2024

Silicon Photonic 2.5D Interposer Networks for Overcoming Communication Bottlenecks in Scale-out Machine Learning Hardware Accelerators.
CoRR, 2024

Accelerating Neural Networks for Large Language Models and Graph Processing with Silicon Photonics.
CoRR, 2024

2023
Special Issue on the 2023 International Symposium on Networks-on-Chip (NOCS 2023).
IEEE Des. Test, December, 2023

GHOST: A Graph Neural Network Accelerator using Silicon Photonics.
ACM Trans. Embed. Comput. Syst., October, 2023

AdEle+: An Adaptive Congestion-and-Energy-Aware Elevator Selection for Partially Connected 3D Networks-on-Chip.
IEEE Trans. Computers, August, 2023

On the Impact of Uncertainties in Silicon-Photonic Neural Networks.
IEEE Des. Test, April, 2023

OISA: Architecting an Optical In-Sensor Accelerator for Efficient Visual Computing.
CoRR, 2023

COMET: A Cross-Layer Optimized Optical Phase Change Main Memory Architecture.
CoRR, 2023

Compact and Low-Loss PCM-based Silicon Photonic MZIs for Photonic Neural Networks.
CoRR, 2023

SerIOS: Enhancing Hardware Security in Integrated Optoelectronic Systems.
CoRR, 2023

Analysis of Optical Loss and Crosstalk Noise in MZI-based Coherent Photonic Neural Networks.
CoRR, 2023

A Survey on Optical Phase-Change Memory: The Promise and Challenges.
IEEE Access, 2023

RISA: Round-Robin Intra-Rack Friendly Scheduling Algorithm for Disaggregated Datacenters.
Proceedings of the SC '23 Workshops of The International Conference on High Performance Computing, 2023

PARS: A Power-Aware and Reliable Control Plane for Silicon Photonic Switch Fabrics.
Proceedings of the International Conference on Photonics in Switching and Computing, 2023

Integrated Photonic AI Accelerators Under Hardware Security Attacks: Impacts and Countermeasures.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

TRINE: A Tree-Based Silicon Photonic Interposer Network for Energy-Efficient 2.5D Machine Learning Acceleration.
Proceedings of the 16th International Workshop on Network on Chip Architectures, 2023

Cross-Layer Design for AI Acceleration with Non-Coherent Optical Computing.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

Design Space Exploration for PCM-based Photonic Memory.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

TRON: Transformer Neural Network Acceleration with Non-Coherent Silicon Photonics.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

Machine Learning Accelerators in 2.5D Chiplet Platforms with Silicon Photonics.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022
Silicon Photonic Microring Resonators: A Comprehensive Design-Space Exploration and Optimization Under Fabrication-Process Variations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Photonic Networks-on-Chip Employing Multilevel Signaling: A Cross-Layer Comparative Study.
ACM J. Emerg. Technol. Comput. Syst., 2022

Characterizing Coherent Integrated Photonic Neural Networks under Imperfections.
CoRR, 2022

Characterization and Optimization of Integrated Silicon-Photonic Neural Networks under Fabrication-Process Variations.
CoRR, 2022

CHAMP: Coherent Hardware-Aware Magnitude Pruning of Integrated Photonic Neural Networks.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2022

RecLight: A Recurrent Neural Network Accelerator with Integrated Silicon Photonics.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

Pruning Coherent Integrated Photonic Neural Networks Using the Lottery Ticket Hypothesis.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

ReSiPI: A Reconfigurable Silicon-Photonic 2.5D Chiplet Network with PCMs for Energy-Efficient Interposer Communication.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

A Silicon Photonic Accelerator for Convolutional Neural Networks with Heterogeneous Quantization.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

LoCI: An Analysis of the Impact of Optical Loss and Crosstalk Noise in Integrated Silicon-Photonic Neural Networks.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

DeFT: A Deadlock-Free and Fault-Tolerant Routing Algorithm for 2.5D Chiplet Networks.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

SONIC: A Sparse Neural Network Inference Accelerator with Silicon Photonics for Energy-Efficient Deep Learning.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021
ARXON: A Framework for Approximate Communication Over Photonic Networks-on-Chip.
IEEE Trans. Very Large Scale Integr. Syst., 2021

ROBIN: A Robust Optical Binary Neural Network Accelerator.
ACM Trans. Embed. Comput. Syst., 2021

A Survey on Silicon Photonics for Deep Learning.
ACM J. Emerg. Technol. Comput. Syst., 2021

HyCo: A Low-Latency Hybrid Control Plane for Optical Interconnection Networks.
Proceedings of the IEEE International Workshop on Rapid System Prototyping, 2021

Optimizing Coherent Integrated Photonic Neural Networks under Random Uncertainties.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2021

Modeling Silicon-Photonic Neural Networks under Uncertainties.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

AdEle: An Adaptive Congestion-and-Energy-Aware Elevator Selection for Partially Connected 3D NoCs.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

CrossLight: A Cross-Layer Optimized Silicon Photonic Neural Network Accelerator.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020
A Survey of Silicon Photonics for Energy-Efficient Manycore Computing.
IEEE Des. Test, 2020

LORAX: Loss-Aware Approximations for Energy-Efficient Silicon Photonic Networks-on-Chip.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

Silicon Photonic Microring Resonators: Design Optimization Under Fabrication Non-Uniformity.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Opportunities for Cross-Layer Design in High-Performance Computing Systems with Integrated Silicon Photonic Networks.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
Guest Editors' Introduction: Emerging Networks-on-Chip Designs, Technologies, and Applications.
ACM J. Emerg. Technol. Comput. Syst., 2019

Wavelength-Routed Optical NoCs: Design and EDA - State of the Art and Future Directions: Invited Paper.
Proceedings of the International Conference on Computer-Aided Design, 2019

2018
DeEPeR: Enhancing Performance and Reliability in Chip-Scale Optical Interconnection Networks.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

Silicon Photonic Interconnects: Minimizing the Controller Latency.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

2017
HypAp: A Hypervolume-Based Approach for Refining the Design of Embedded Systems.
IEEE Embed. Syst. Lett., 2017

2016
Coherent and Incoherent Crosstalk Noise Analyses in Interchip/Intrachip Optical Interconnection Networks.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Design and Modelling of a Low-Latency Centralized Controller for Optical Integrated Networks.
IEEE Commun. Lett., 2016

Photonic integrated circuits: A study on process variations.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2016

Modeling fabrication non-uniformity in chip-scale silicon photonic interconnects.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
An Inter/Intra-Chip Optical Network for Manycore Processors.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Actively Alleviate Power Gating-Induced Power/Ground Noise Using Parasitic Capacitance of On-Chip Memories in MPSoC.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Crosstalk Noise in WDM-Based Optical Networks-on-Chip: A Formal Study and Comparison.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Fat-Tree-Based Optical Interconnection Networks Under Crosstalk Noise Constraint.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Coherent crosstalk noise analyses in ring-based optical interconnects.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
UNION: A Unified Inter/Intrachip Optical Network for Chip Multiprocessors.
IEEE Trans. Very Large Scale Integr. Syst., 2014

System-Level Modeling and Analysis of Thermal Effects in WDM-Based Optical Networks-on-Chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Systematic Analysis of Crosstalk Noise in Folded-Torus-Based Optical Networks-on-Chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Floorplan Optimization of Fat-Tree-Based Networks-on-Chip for Chip Multiprocessors.
IEEE Trans. Computers, 2014

SUOR: Sectioned Undirectional Optical Ring for Chip Multiprocessor.
ACM J. Emerg. Technol. Comput. Syst., 2014

On-chip sensor networks for soft-error tolerant real-time multiprocessor systems-on-chip.
ACM J. Emerg. Technol. Comput. Syst., 2014

A Case Study of Signal-to-Noise Ratio in Ring-Based Optical Networks-on-Chip.
IEEE Des. Test, 2014

CLAP: a crosstalk and loss analysis platform for optical interconnects.
Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014

2013
System-Level Modeling and Analysis of Thermal Effects in Optical Networks-on-Chip.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Formal Worst-Case Analysis of Crosstalk Noise in Mesh-Based Optical Networks-on-Chip.
IEEE Trans. Very Large Scale Integr. Syst., 2013

3-D Mesh-Based Optical Network-on-Chip for Multiprocessor System-on-Chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

System-level analysis of mesh-based hybrid optical-electronic network-on-chip.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Active power-gating-induced power/ground noise alleviation using parasitic capacitance of on-chip memories.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
A Torus-Based Hierarchical Optical-Electronic Network-on-Chip for Multiprocessor System-on-Chip.
ACM J. Emerg. Technol. Comput. Syst., 2012

2011
Modeling and Analysis of Thermal Effects in Optical Networks-on-Chip.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

A NoC Traffic Suite Based on Real Applications.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

A Hardware-Software Collaborated Method for Soft-Error Tolerant MPSoC.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

2010
UNION: A unified inter/intra-chip optical network for chip multiprocessors.
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures, 2010

Crosstalk noise and bit error rate analysis for optical network-on-chip.
Proceedings of the 47th Design Automation Conference, 2010


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