Zhehui Wang

Orcid: 0000-0002-7139-724X

According to our database¹, Zhehui Wang authored at least 68 papers between 2011 and 2026.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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Links

On csauthors.net:

Bibliography

2026

Privacy-preserving cloud-based dermatological image processing for medical applications: a review.

[BibT_eX]

[DOI]

J. Cloud Comput., December, 2026

Is quantum optimization ready? An effort towards neural network compression using adiabatic quantum computing.

[BibT_eX]

[DOI]

Zhehui Wang

Benjamin Chen Ming Choong

Future Gener. Comput. Syst., 2026

2025

A Machine Learning-Driven Solution for Denoising Inertial Confinement Fusion Images.

[BibT_eX]

[DOI]

Mariana Alvarado Alvarez

CoRR, November, 2025

RBFleX-NAS: Training-Free Neural Architecture Search Using Radial Basis Function Kernel and Hyperparameter Detection.

[BibT_eX]

[DOI]

IEEE Trans. Neural Networks Learn. Syst., June, 2025

RBFleX-NAS: Training-Free Neural Architecture Search Using Radial Basis Function Kernel and Hyperparameter Detection.

[BibT_eX]

[DOI]

CoRR, March, 2025

Enabling Energy-Efficient Deployment of Large Language Models on Memristor Crossbar: A Synergy of Large and Small.

[BibT_eX]

[DOI]

IEEE Trans. Pattern Anal. Mach. Intell., February, 2025

Coflex: Enhancing HW-NAS with Sparse Gaussian Processes for Efficient and Scalable DNN Accelerator Design.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2025

2024

Optimizing for In-Memory Deep Learning With Emerging Memory Technology.

[BibT_eX]

[DOI]

IEEE Trans. Neural Networks Learn. Syst., November, 2024

Efficient Spiking Neural Networks With Radix Encoding.

[BibT_eX]

[DOI]

IEEE Trans. Neural Networks Learn. Syst., March, 2024

EDCompress: Energy-Aware Model Compression for Dataflows.

[BibT_eX]

[DOI]

IEEE Trans. Neural Networks Learn. Syst., January, 2024

IMI: In-memory Multi-job Inference Acceleration for Large Language Models.

[BibT_eX]

[DOI]

Proceedings of the 53rd International Conference on Parallel Processing, 2024

2023

PATCorrect: Non-autoregressive Phoneme-augmented Transformer for ASR Error Correction.

[BibT_eX]

[DOI]

Proceedings of the 24th Annual Conference of the International Speech Communication Association, 2023

MA-BERT: Towards Matrix Arithmetic-only BERT Inference by Eliminating Complex Non-Linear Functions.

[BibT_eX]

[DOI]

Proceedings of the Eleventh International Conference on Learning Representations, 2023

2022

E3NE: An End-to-End Framework for Accelerating Spiking Neural Networks With Emerging Neural Encoding on FPGAs.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2022

Machine Learning for Detection of 3D Features using sparse X-ray data.

[BibT_eX]

[DOI]

Bradley T. Wolfe

Michael J. Falato

Xinhua Zhang

Nga T. T. Nguyen-Fotiadis

CoRR, 2022

A Resource-efficient Spiking Neural Network Accelerator Supporting Emerging Neural Encoding.

[BibT_eX]

[DOI]

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021

Asynchronous and Load-Balanced Union-Find for Distributed and Parallel Scientific Data Visualization and Analysis.

[BibT_eX]

[DOI]

IEEE Trans. Vis. Comput. Graph., 2021

Reduce Loss and Crosstalk in Integrated Silicon-Photonic Multistage Switching Fabrics Through Multichip Partition.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Simulating 50 keV X-ray Photon Detection in Silicon with a Down-Conversion Layer.

[BibT_eX]

[DOI]

Sensors, 2021

Evolutionary Multi-Objective Model Compression for Deep Neural Networks.

[BibT_eX]

[DOI]

IEEE Comput. Intell. Mag., 2021

2020

Chip-Specific Power Delivery and Consumption Co-Management for Process-Variation-Aware Manycore Systems Using Reinforcement Learning.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2020

Multidomain Inter/Intrachip Silicon Photonic Networks for Energy-Efficient Rack-Scale Computing Systems.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

A Cross-Layer Optimization Framework for Integrated Optical Switches in Data Centers.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

CAMON: Low-Cost Silicon Photonic Chiplet for Manycore Processors.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Modeling and Analysis of Optical Modulators Based on Free-Carrier Plasma Dispersion Effect.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

EDCompress: Energy-Aware Model Compression with Dataflow.

[BibT_eX]

[DOI]

CoRR, 2020

Distributed Asynchronous Union-Find for Scalable Feature Tracking.

[BibT_eX]

[DOI]

CoRR, 2020

NCPower: Power Modelling for NVM-based Neuromorphic Chip.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Neuromorphic Systems, 2020

2019

Crosstalk Noise Reduction Through Adaptive Power Control in Inter/Intra-Chip Optical Networks.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

The ISTI Rapid Response on Exploring Cloud Computing 2018.

[BibT_eX]

[DOI]

CoRR, 2019

Scalable Low-Power High-Performance Rack-Scale Optical Network.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE/ACM Workshop on Photonics-Optics Technology Oriented Networking, 2019

Systematic Exploration of High-Radix Integrated Silicon Photonic Switches for Datacenters.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer-Aided Design, 2019

2018

A Comprehensive Electro-Optical Model for Silicon Photonic Switches.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

RSON: An inter/intra-chip silicon photonic network for rack-scale computing systems.

[BibT_eX]

[DOI]

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017

Energy-Efficient Power Delivery System Paradigms for Many-Core Processors.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

MOCA: an Inter/Intra-Chip Optical Network for Memory.

[BibT_eX]

[DOI]

Proceedings of the 54th Annual Design Automation Conference, 2017

Modular reinforcement learning for self-adaptive energy efficiency optimization in multicore system.

[BibT_eX]

[DOI]

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016

Improve Chip Pin Performance Using Optical Interconnects.

[BibT_eX]

[DOI]

Rafael Kioji Vivas Maeda

Haoran Li

IEEE Trans. Very Large Scale Integr. Syst., 2016

A Holistic Modeling and Analysis of Optical-Electrical Interfaces for Inter/Intra-chip Interconnects.

[BibT_eX]

[DOI]

Rafael Kioji Vivas Maeda

IEEE Trans. Very Large Scale Integr. Syst., 2016

An Adaptive Process-Variation-Aware Technique for Power-Gating-Induced Power/Ground Noise Mitigation in MPSoC.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

Coherent and Incoherent Crosstalk Noise Analyses in Interchip/Intrachip Optical Interconnection Networks.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

Inter/intra-chip optical interconnection network: opportunities, challenges, and implementations.

[BibT_eX]

[DOI]

Proceedings of the Tenth IEEE/ACM International Symposium on Networks-on-Chip, 2016

JADE: a Heterogeneous Multiprocessor System Simulation Platform Using Recorded and Statistical Application Models.

[BibT_eX]

[DOI]

Proceedings of the 1st International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems, 2016

2015

An Inter/Intra-Chip Optical Network for Manycore Processors.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

Actively Alleviate Power Gating-Induced Power/Ground Noise Using Parasitic Capacitance of On-Chip Memories in MPSoC.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

Crosstalk Noise in WDM-Based Optical Networks-on-Chip: A Formal Study and Comparison.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

Fat-Tree-Based Optical Interconnection Networks Under Crosstalk Noise Constraint.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

An Analytical Study of Power Delivery Systems for Many-Core Processors Using On-Chip and Off-Chip Voltage Regulators.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Adaptively tolerate power-gating-induced power/ground noise under process variations.

[BibT_eX]

[DOI]

Rafael Kioji Vivas Maeda

Zhifei Wang

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Coherent crosstalk noise analyses in ring-based optical interconnects.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Alleviate chip I/O pin constraints for multicore processors through optical interconnects.

[BibT_eX]

[DOI]

Rafael Kioji Vivas Maeda

Xiaowen Wu

Yaoyao Ye

Qinfen Hao

Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014

System-Level Modeling and Analysis of Thermal Effects in WDM-Based Optical Networks-on-Chip.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Systematic Analysis of Crosstalk Noise in Folded-Torus-Based Optical Networks-on-Chip.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Floorplan Optimization of Fat-Tree-Based Networks-on-Chip for Chip Multiprocessors.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2014

SUOR: Sectioned Undirectional Optical Ring for Chip Multiprocessor.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2014

On-chip sensor networks for soft-error tolerant real-time multiprocessor systems-on-chip.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2014

A Case Study of Signal-to-Noise Ratio in Ring-Based Optical Networks-on-Chip.

[BibT_eX]

[DOI]

IEEE Des. Test, 2014

CLAP: a crosstalk and loss analysis platform for optical interconnects.

[BibT_eX]

[DOI]

Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014

Characterizing power delivery systems with on/off-chip voltage regulators for many-core processors.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

A systematic network-on-chip traffic modeling and generation methodology.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

2013

System-Level Modeling and Analysis of Thermal Effects in Optical Networks-on-Chip.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2013

Formal Worst-Case Analysis of Crosstalk Noise in Mesh-Based Optical Networks-on-Chip.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2013

3-D Mesh-Based Optical Network-on-Chip for Multiprocessor System-on-Chip.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

System-level analysis of mesh-based hybrid optical-electronic network-on-chip.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Active power-gating-induced power/ground noise alleviation using parasitic capacitance of on-chip memories.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

2011

Modeling and Analysis of Thermal Effects in Optical Networks-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

A NoC Traffic Suite Based on Real Applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

A Hardware-Software Collaborated Method for Soft-Error Tolerant MPSoC.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

Zhehui Wang

Timeline

Legend:

Links

On csauthors.net:

Bibliography

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