Peng Yang

Orcid: 0000-0003-3675-3365

Affiliations:
  • Hong Kong University of Science and Technology, Department of Electronic and Computer Engineering, Hong Kong


According to our database1, Peng Yang authored at least 30 papers between 2014 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2020
Multidomain Inter/Intrachip Silicon Photonic Networks for Energy-Efficient Rack-Scale Computing Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

A Cross-Layer Optimization Framework for Integrated Optical Switches in Data Centers.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Modeling and Analysis of Optical Modulators Based on Free-Carrier Plasma Dispersion Effect.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

2019
Collaborative Power Management Through Knowledge Sharing Among Multiple Devices.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Crosstalk Noise Reduction Through Adaptive Power Control in Inter/Intra-Chip Optical Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

2018
A Systematic and Realistic Network-on-Chip Traffic Modeling and Generation Technique for Emerging Many-Core Systems.
IEEE Trans. Multi Scale Comput. Syst., 2018

Workload-Aware Adaptive Power Delivery System Management for Many-Core Processors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

A Comprehensive Electro-Optical Model for Silicon Photonic Switches.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

RSON: An inter/intra-chip silicon photonic network for rack-scale computing systems.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Multi-device collaborative management through knowledge sharing.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017
Energy-Efficient Power Delivery System Paradigms for Many-Core Processors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Adaptive power delivery system management for many-core processors with on/off-chip voltage regulators.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

MOCA: an Inter/Intra-Chip Optical Network for Memory.
Proceedings of the 54th Annual Design Automation Conference, 2017

Modular reinforcement learning for self-adaptive energy efficiency optimization in multicore system.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
Improve Chip Pin Performance Using Optical Interconnects.
IEEE Trans. Very Large Scale Integr. Syst., 2016

A Holistic Modeling and Analysis of Optical-Electrical Interfaces for Inter/Intra-chip Interconnects.
IEEE Trans. Very Large Scale Integr. Syst., 2016

An Adaptive Process-Variation-Aware Technique for Power-Gating-Induced Power/Ground Noise Mitigation in MPSoC.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Coherent and Incoherent Crosstalk Noise Analyses in Interchip/Intrachip Optical Interconnection Networks.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Alleviate Chip Pin Constraint for Multicore Processor by On/Off-Chip Power Delivery System Codesign.
ACM J. Emerg. Technol. Comput. Syst., 2016

Inter/intra-chip optical interconnection network: opportunities, challenges, and implementations.
Proceedings of the Tenth IEEE/ACM International Symposium on Networks-on-Chip, 2016

JADE: a Heterogeneous Multiprocessor System Simulation Platform Using Recorded and Statistical Application Models.
Proceedings of the 1st International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems, 2016

2015
Crosstalk Noise in WDM-Based Optical Networks-on-Chip: A Formal Study and Comparison.
IEEE Trans. Very Large Scale Integr. Syst., 2015

An Analytical Study of Power Delivery Systems for Many-Core Processors Using On-Chip and Off-Chip Voltage Regulators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Memory Access Analysis of Many-core System with Abundant Bandwidth.
Proceedings of the IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2015

Adaptively tolerate power-gating-induced power/ground noise under process variations.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Coherent crosstalk noise analyses in ring-based optical interconnects.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Alleviate chip I/O pin constraints for multicore processors through optical interconnects.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
System-Level Modeling and Analysis of Thermal Effects in WDM-Based Optical Networks-on-Chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

A Case Study of Signal-to-Noise Ratio in Ring-Based Optical Networks-on-Chip.
IEEE Des. Test, 2014

CLAP: a crosstalk and loss analysis platform for optical interconnects.
Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014


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