Yvain Thonnart

According to our database1, Yvain Thonnart authored at least 52 papers between 2007 and 2021.

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Bibliography

2021
PROWAVES: Proactive Runtime Wavelength Selection for Energy-Efficient Photonic NoCs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management.
IEEE J. Solid State Circuits, 2021

Architecting Optically-Controlled Phase Change Memory.
CoRR, 2021

Designing a Multi-Chiplet Manycore System using the POPSTAR Optical NoC Architecture (Invited).
Proceedings of the ACM/IEEE International Workshop on System Level Interconnect Prediction, 2021

SE2: Going Remote: Challenges and Opportunities to Remote Learning, Work, and Collaboration.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2020
2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm<sup>2</sup> Inter-Chiplet Interconnects and 156mW/mm<sup>2</sup>@ 82%-Peak-Efficiency DC-DC Converters.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

19.2 A 110mK 295µW 28nm FDSOI CMOS Quantum Integrated Circuit with a 2.8GHz Excitation and nA Current Sensing of an On-Chip Double Quantum Dot.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

POPSTAR: a Robust Modular Optical NoC Architecture for Chiplet-based 3D Integrated Systems.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

System-level Evaluation of Chip-Scale Silicon Photonic Networks for Emerging Data-Intensive Applications.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
WAVES: Wavelength Selection for Power-Efficient 2.5D-Integrated Photonic NoCs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Latency Improvement of an Industrial SoC System Interconnect using an Asynchronous NoC Backbone.
Proceedings of the 25th IEEE International Symposium on Asynchronous Circuits and Systems, 2019

2018
A 10Gb/s Si-photonic transceiver with 150μW 120μs-lock-time digitally supervised analog microring wavelength stabilization for 1Tb/s/mm<sup>2</sup> Die-to-Die Optical Networks.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2017
A 4 × 4 × 2 Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links.
IEEE J. Solid State Circuits, 2017

In-situ Fmax/Vmin tracking for energy efficiency and reliability optimization.
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017

2016
Efficiency Optimization of Silicon Photonic Links in 65-nm CMOS and 28-nm FDSOI Technology Nodes.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Coherent and Incoherent Crosstalk Noise Analyses in Interchip/Intrachip Optical Interconnection Networks.
IEEE Trans. Very Large Scale Integr. Syst., 2016

10 Gbps, 560 fJ/b TIA and modulator driver for optical networks-on-chip in CMOS 65nm.
Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016

8.1 A 4×4×2 homogeneous scalable 3D network-on-chip circuit with 326MFlit/s 0.66pJ/b robust and fault-tolerant asynchronous 3D links.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015
A 460 MHz at 397 mV, 2.6 GHz at 1.3 V, 32 bits VLIW DSP Embedding F MAX Tracking.
IEEE J. Solid State Circuits, 2015

Interconnect Challenges for 3D Multi-cores: From 3D Network-on-Chip to Cache Interconnects.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Fine-grain DVFS and AVFS techniques for complex SoC design: An overview of architectural solutions through technology nodes.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Coherent crosstalk noise analyses in ring-based optical interconnects.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Complementary communication path for energy efficient on-chip optical interconnects.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Two-phase protocol converters for 3D asynchronous 1-of-n data links.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

3D advanced integration technology for heterogeneous systems.
Proceedings of the 2015 International 3D Systems Integration Conference, 2015

2014
A Fine-Grain Variation-Aware Dynamic Vdd-Hopping AVFS Architecture on a 32 nm GALS MPSoC.
IEEE J. Solid State Circuits, 2014

Introduction to the special session on "Silicon photonic interconnects: an illusion or a realistic solution?".
Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014

Technology assessment of silicon interposers for manycore SoCs: Active, passive, or optical?
Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014


2013
An Iterative Computational Technique for Performance Evaluation of Networks-on-Chip.
IEEE Trans. Computers, 2013

Fine grain multi-VT co-integration methodology in UTBB FD-SOI technology.
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

A fine grain variation-aware dynamic Vdd-hopping AVFS architecture on a 32nm GALS MPSoC.
Proceedings of the ESSCIRC 2013, 2013


2012
A Pseudo-Synchronous Implementation Flow for WCHB QDI Asynchronous Circuits.
Proceedings of the 18th IEEE International Symposium on Asynchronous Circuits and Systems, 2012

2011
3D NoC using through silicon Via: An asynchronous implementation.
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

2010
Distributed Sequencing for Resource Sharing in Multi-applicative Heterogeneous NoC Platforms.
Proceedings of the NOCS 2010, 2010

A 477mW NoC-based digital baseband for MIMO 4G SDR.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

A Markov chain based method for NoC end-to-end latency evaluation.
Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

A fully-asynchronous low-power framework for GALS NoC integration.
Proceedings of the Design, Automation and Test in Europe, 2010

An analytical method for evaluating Network-on-Chip performance.
Proceedings of the Design, Automation and Test in Europe, 2010

2009
Power Reduction of Asynchronous Logic Circuits Using Activity Detection.
IEEE Trans. Very Large Scale Integr. Syst., 2009

An Asynchronous Power Aware and Adaptive NoC Based Circuit.
IEEE J. Solid State Circuits, 2009

Design-for-test approach of an asynchronous network-on-chip architecture and its associated test pattern generation and application.
IET Comput. Digit. Tech., 2009

A Communication and configuration controller for NoC based reconfigurable data flow architecture.
Proceedings of the Third International Symposium on Networks-on-Chips, 2009

An Open and Reconfigurable Platform for 4G Telecommunication: Concepts and Application.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

Design and Implementation of a GALS Adapter for ANoC Based Architectures.
Proceedings of the 15th IEEE Symposium on Asynchronous Circuits and Systems, 2009

2008
A Design-for-Test Implementation of an Asynchronous Network-on-Chip Architecture and its Associated Test Pattern Generation and Application.
Proceedings of the Second International Symposium on Networks-on-Chips, 2008

Quantitative Evaluation in Embedded System Design: Validation of Multiprocessor Multithreaded Architectures.
Proceedings of the Design, Automation and Test in Europe, 2008

Automatic Power Regulation Based on an Asynchronous Activity Detection and its Application to ANOC Node Leakage Reduction.
Proceedings of the 14th IEEE International Symposium on Asynchronous Circuits and Systems, 2008

2007
Implementation of a Design-for-Test Architecture for Asynchronous Networks-on-Chip.
Proceedings of the First International Symposium on Networks-on-Chips, 2007

ASC, a SystemC Extension for Modeling Asynchronous Systems, and Its Application to an Asynchronous NoC.
Proceedings of the First International Symposium on Networks-on-Chips, 2007

Formal Verification of CHP Specifications with CADP Illustration on an Asynchronous Network-on-Chip.
Proceedings of the 13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2007), 2007


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