Zhe Wang

Affiliations:
  • Huawei Technologies Co. Ltd.
  • Hong Kong University of Science and Technology, Department of Electronic and Computer Engineering, Hong Kong (former)


According to our database1, Zhe Wang authored at least 32 papers between 2013 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2019
Collaborative Power Management Through Knowledge Sharing Among Multiple Devices.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

2018
A Systematic and Realistic Network-on-Chip Traffic Modeling and Generation Technique for Emerging Many-Core Systems.
IEEE Trans. Multi Scale Comput. Syst., 2018

Workload-Aware Adaptive Power Delivery System Management for Many-Core Processors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Multi-device collaborative management through knowledge sharing.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017
Energy-Efficient Power Delivery System Paradigms for Many-Core Processors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Fast and Accurate Exploration of Multi-level Caches Using Hierarchical Reuse Distance.
Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017

Adaptive power delivery system management for many-core processors with on/off-chip voltage regulators.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

MOCA: an Inter/Intra-Chip Optical Network for Memory.
Proceedings of the 54th Annual Design Automation Conference, 2017

Modular reinforcement learning for self-adaptive energy efficiency optimization in multicore system.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
Improve Chip Pin Performance Using Optical Interconnects.
IEEE Trans. Very Large Scale Integr. Syst., 2016

A Holistic Modeling and Analysis of Optical-Electrical Interfaces for Inter/Intra-chip Interconnects.
IEEE Trans. Very Large Scale Integr. Syst., 2016

An Adaptive Process-Variation-Aware Technique for Power-Gating-Induced Power/Ground Noise Mitigation in MPSoC.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Coherent and Incoherent Crosstalk Noise Analyses in Interchip/Intrachip Optical Interconnection Networks.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Alleviate Chip Pin Constraint for Multicore Processor by On/Off-Chip Power Delivery System Codesign.
ACM J. Emerg. Technol. Comput. Syst., 2016

JADE: a Heterogeneous Multiprocessor System Simulation Platform Using Recorded and Statistical Application Models.
Proceedings of the 1st International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems, 2016

2015
An Inter/Intra-Chip Optical Network for Manycore Processors.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Actively Alleviate Power Gating-Induced Power/Ground Noise Using Parasitic Capacitance of On-Chip Memories in MPSoC.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Crosstalk Noise in WDM-Based Optical Networks-on-Chip: A Formal Study and Comparison.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Fat-Tree-Based Optical Interconnection Networks Under Crosstalk Noise Constraint.
IEEE Trans. Very Large Scale Integr. Syst., 2015

An Analytical Study of Power Delivery Systems for Many-Core Processors Using On-Chip and Off-Chip Voltage Regulators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Memory Access Analysis of Many-core System with Abundant Bandwidth.
Proceedings of the IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2015

Adaptively tolerate power-gating-induced power/ground noise under process variations.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Alleviate chip I/O pin constraints for multicore processors through optical interconnects.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
System-Level Modeling and Analysis of Thermal Effects in WDM-Based Optical Networks-on-Chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Systematic Analysis of Crosstalk Noise in Folded-Torus-Based Optical Networks-on-Chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Floorplan Optimization of Fat-Tree-Based Networks-on-Chip for Chip Multiprocessors.
IEEE Trans. Computers, 2014

A Case Study on the Communication and Computation Behaviors of Real Applications in NoC-Based MPSoCs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Characterizing power delivery systems with on/off-chip voltage regulators for many-core processors.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

A systematic network-on-chip traffic modeling and generation methodology.
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

2013
3-D Mesh-Based Optical Network-on-Chip for Multiprocessor System-on-Chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

System-level analysis of mesh-based hybrid optical-electronic network-on-chip.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Active power-gating-induced power/ground noise alleviation using parasitic capacitance of on-chip memories.
Proceedings of the Design, Automation and Test in Europe, 2013


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