Yaoyao Ye

According to our database1, Yaoyao Ye authored at least 37 papers between 2009 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2019
A thermal-sensitive design of a 3D torus-based optical NoC architecture.
Integration, 2019

2018
Thermal-Sensor-Based Occupancy Detection for Smart Buildings Using Machine-Learning Methods.
ACM Trans. Design Autom. Electr. Syst., 2018

A Learning-Based Thermal-Sensitive Power Optimization Approach for Optical NoCs.
JETC, 2018

Fine-Grained Task-Level Parallel and Low Power H.264 Decoding in Multi-Core Systems.
Proceedings of the 24th IEEE International Conference on Parallel and Distributed Systems, 2018

User Experience-Enhanced and Energy-Efficient Task Scheduling on Heterogeneous Multi-Core Mobile Systems.
Proceedings of the 24th IEEE International Conference on Parallel and Distributed Systems, 2018

Communication optimization for thermal reliable optical network-on-chip: work-in-progress.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2018

2017
Comprehensive detection of counterfeit ICs via on-chip sensor and post-fabrication authentication policy.
Proceedings of the 14th International Conference on Synthesis, 2017

Thermal-sensitive design and power optimization for a 3D torus-based optical NoC.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

2015
An Inter/Intra-Chip Optical Network for Manycore Processors.
IEEE Trans. VLSI Syst., 2015

Actively Alleviate Power Gating-Induced Power/Ground Noise Using Parasitic Capacitance of On-Chip Memories in MPSoC.
IEEE Trans. VLSI Syst., 2015

Crosstalk Noise in WDM-Based Optical Networks-on-Chip: A Formal Study and Comparison.
IEEE Trans. VLSI Syst., 2015

User Experience Enhanced Task Scheduling and Processor Frequency Scaling for Energy-Sensitive Mobile Devices.
Proceedings of the 17th IEEE International Conference on High Performance Computing and Communications, 2015

Efficient SAT-based application mapping and scheduling on multiprocessor systems for throughput maximization.
Proceedings of the 2015 International Conference on Compilers, 2015

Alleviate chip I/O pin constraints for multicore processors through optical interconnects.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
UNION: A Unified Inter/Intrachip Optical Network for Chip Multiprocessors.
IEEE Trans. VLSI Syst., 2014

System-Level Modeling and Analysis of Thermal Effects in WDM-Based Optical Networks-on-Chip.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2014

Systematic Analysis of Crosstalk Noise in Folded-Torus-Based Optical Networks-on-Chip.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2014

Floorplan Optimization of Fat-Tree-Based Networks-on-Chip for Chip Multiprocessors.
IEEE Trans. Computers, 2014

SUOR: Sectioned Undirectional Optical Ring for Chip Multiprocessor.
JETC, 2014

On-chip sensor networks for soft-error tolerant real-time multiprocessor systems-on-chip.
JETC, 2014

CLAP: a crosstalk and loss analysis platform for optical interconnects.
Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014

2013
System-Level Modeling and Analysis of Thermal Effects in Optical Networks-on-Chip.
IEEE Trans. VLSI Syst., 2013

Formal Worst-Case Analysis of Crosstalk Noise in Mesh-Based Optical Networks-on-Chip.
IEEE Trans. VLSI Syst., 2013

3-D Mesh-Based Optical Network-on-Chip for Multiprocessor System-on-Chip.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2013

A formal study on topology and floorplan characteristics of mesh and torus-based optical networks-on-chip.
Microprocessors and Microsystems - Embedded Hardware Design, 2013

System-level analysis of mesh-based hybrid optical-electronic network-on-chip.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Active power-gating-induced power/ground noise alleviation using parasitic capacitance of on-chip memories.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
A Torus-Based Hierarchical Optical-Electronic Network-on-Chip for Multiprocessor System-on-Chip.
JETC, 2012

2011
Satisfiability Modulo Graph Theory for Task Mapping and Scheduling on Multiprocessor Systems.
IEEE Trans. Parallel Distrib. Syst., 2011

Coroutine-Based Synthesis of Efficient Embedded Software From SystemC Models.
Embedded Systems Letters, 2011

Modeling and Analysis of Thermal Effects in Optical Networks-on-Chip.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

A NoC Traffic Suite Based on Real Applications.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

A Hardware-Software Collaborated Method for Soft-Error Tolerant MPSoC.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

2010
UNION: A unified inter/intra-chip optical network for chip multiprocessors.
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures, 2010

A Hierarchical Hybrid Optical-Electronic Network-on-Chip.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Crosstalk noise and bit error rate analysis for optical network-on-chip.
Proceedings of the 47th Design Automation Conference, 2010

2009
3D optical networks-on-chip (NoC) for multiprocessor systems-on-chip (MPSoC).
Proceedings of the IEEE International Conference on 3D System Integration, 2009


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