Felice Balarin

According to our database, Felice Balarin authored at least 62 papers between 1992 and 2009.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of four.

2009

Memory subsystem simulation in software TLM/T models.

Eric Cheung, Harry Hsieh, Felice Balarin

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

Fast and accurate performance simulation of embedded software for MPSoC.

Eric Cheung, Harry Hsieh, Felice Balarin

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

Partial order method for timed simulation of system-level MPSoC designs.

Eric Cheung, Harry Hsieh, Felice Balarin

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008

Software optimization for MPSoC: a mpeg-2 decoder case study.

Eric Cheung, Harry Hsieh, Felice Balarin

Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, 2008

2007

Specification, Synthesis, and Simulation of Transactor Processes.

Felice Balarin, Roberto Passerone

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Automatic buffer sizing for rate-constrained KPN applications on multiprocessor system-on-chip.

Eric Cheung, Harry Hsieh, Felice Balarin

Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2007

Framework for fast and accurate performance simulation of multiprocessor systems.

Eric Cheung, Harry Hsieh, Felice Balarin

Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2007

2006

Verification Approach of Metropolis Design Framework for Embedded Systems.

Xi Chen, Harry Hsieh, Felice Balarin

Int. J. Parallel Program., 2006

Communication and co-simulation infrastructure for heterogeneous system integration.

Guang Yang, Xi Chen, Felice Balarin, Harry Hsieh, Alberto L. Sangiovanni-Vincentelli

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Functional verification methodology based on formal interface specification and transactor generation.

Felice Balarin, Roberto Passerone

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005

A formal approach to system level design: metamodels and unified design environments.

Felice Balarin, Roberto Passerone, Alessandro Pinto, Alberto L. Sangiovanni-Vincentelli

Proceedings of the 3rd ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2005), 2005

Assertion-Based Design Exploration of DVS in Network Processor Architectures.

Jia Yu, Wei Wu, Xi Chen, Harry Hsieh, Jun Yang, Felice Balarin

Proceedings of the 2005 Design, 2005

2004

Logic of constraints: a quantitative performance and functional constraint formalism.

Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Assertion Based Verification and Analysis of Network Processor Architectures.

Xi Chen, Yan Luo, Harry Hsieh, Laxmi N. Bhuyan, Felice Balarin

Des. Autom. Embed. Syst., 2004

Assertion-based power/performance analysis of network processor architectures.

Jia Yu, Wei Wu, Xi Chen, Harry Hsieh, Jun Yang, Felice Balarin

Proceedings of the Ninth IEEE International High-Level Design Validation and Test Workshop 2004, 2004

Separation of concerns: overhead in modeling and efficient simulation techniques.

Guang Yang, Alberto L. Sangiovanni-Vincentelli, Yosinori Watanabe, Felice Balarin

Proceedings of the EMSOFT 2004, 2004

Utilizing Formal Assertions for System Design of Network Processors.

Xi Chen, Yan Luo, Harry Hsieh, Laxmi N. Bhuyan, Felice Balarin

Proceedings of the 2004 Design, 2004

2003

Formal Verification for Embedded System Designs.

Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe

Des. Autom. Embed. Syst., 2003

Metropolis: An Integrated Electronic System Design Environment.

Felice Balarin, Yosinori Watanabe, Harry Hsieh, Luciano Lavagno, Claudio Passerone, Alberto L. Sangiovanni-Vincentelli

Computer, 2003

Verifying LOC based functional and performance constraints.

Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe

Proceedings of the Eighth IEEE International High-Level Design Validation and Test Workshop 2003, 2003

Automatic Generation of Simulation Monitors from Quantitative Constraint Formula.

Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe

Proceedings of the 2003 Design, 2003

Automatic trace analysis for logic of constraints.

Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe

Proceedings of the 40th Design Automation Conference, 2003

Case Studies of Model Checking for Embedded System Designs.

Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe

Proceedings of the 3rd International Conference on Application of Concurrency to System Design (ACSD 2003), 2003

Simulation Trace Verification for Quantitative Constraints.

Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe

Proceedings of the Embedded Software for SoC, 2003

2002

Formal verification of embedded system designs at multiple levels of abstraction.

Xi Chen, Fang Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe

Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop 2002, 2002

Processes, Interfaces and Platforms. Embedded Software Modeling in Metropolis.

Felice Balarin, Luciano Lavagno, Claudio Passerone, Yosinori Watanabe

Proceedings of the Embedded Software, Second International Conference, 2002

Concurrent execution semantics and sequential simulation algorithms for the metropolis meta-model.

Felice Balarin, Luciano Lavagno, Claudio Passerone, Alberto L. Sangiovanni-Vincentelli, Yosinori Watanabe, Guang Yang

Proceedings of the Tenth International Symposium on Hardware/Software Codesign, 2002

Modeling and Designing Heterogeneous Systems.

Felice Balarin, Luciano Lavagno, Claudio Passerone, Alberto L. Sangiovanni-Vincentelli, Marco Sgroi, Yosinori Watanabe

Proceedings of the Concurrency and Hardware Design, Advances in Petri Nets, 2002

2001

Synchronous approach to the functional equivalence of embeddedsystem implementations.

Harry Hsieh, Felice Balarin, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Scheduling Reactive Task Graphs in Embedded Control Systems.

Marco Di Natale, Alberto L. Sangiovanni-Vincentelli, Felice Balarin

Proceedings of the 7th IEEE Real-Time Technology and Applications Symposium (RTAS 2001), 30 May, 2001

Stars in VCC: Complementing Simulation with Worst-Case Analysis.

Felice Balarin

Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

Constraints specification at higher levels of abstraction.

Felice Balarin, Jerry R. Burch, Luciano Lavagno, Yosinori Watanabe, Roberto Passerone, Alberto L. Sangiovanni-Vincentelli

Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop 2001, 2001

STARS of MPEG decoder: a case study in worst-case analysis of discrete-event systems.

Felice Balarin

Proceedings of the Ninth International Symposium on Hardware/Software Codesign, 2001

2000

Sequential synthesis using S1S.

Adnan Aziz, Felice Balarin, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Refining abstract equivalence analysis for embedded system design.

Harry Hsieh, Felice Balarin

Proceedings of the IEEE International High-Level Design Validation and Test Workshop 2000, 2000

Automatic Abstraction for Worst-Case Analysis of Discrete Systems.

Felice Balarin

Proceedings of the 2000 Design, 2000

Task scheduling with RT constraints.

Marco Di Natale, Alberto L. Sangiovanni-Vincentelli, Felice Balarin

Proceedings of the 37th Conference on Design Automation, 2000

Efficient methods for embedded system design space exploration.

Harry Hsieh, Felice Balarin, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli

Proceedings of the 37th Conference on Design Automation, 2000

1999

Synthesis of software programs for embedded control applications.

Felice Balarin, Massimiliano Chiodo, Paolo Giusto, Harry Hsieh, Attila Jurecska, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli, Ellen Sentovich, Kei Suzuki

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Concurrent Symbolic Verification of Liveness Properties for Interleaved Models.

Felice Balarin

Proceedings of the First International Workshop on Symbolic Model Checking, 1999

Equivalences for Fair Kripke Structures.

Adnan Aziz, Felice Balarin, Vigyan Singhal, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli

Chic. J. Theor. Comput. Sci., 1999

Software Synthesis for Complex Reactive Embedded Systems.

Felice Balarin, Massimiliano Chiodo

Proceedings of the IEEE International Conference On Computer Design, 1999

Synchronous equivalence for embedded systems: a tool for design exploration.

Harry Hsieh, Felice Balarin

Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Worst-case analysis of discrete systems.

Felice Balarin

Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Worst-case analysis of discrete systems based on conditional abstractions.

Felice Balarin

Proceedings of the Seventh International Workshop on Hardware/Software Codesign, 1999

1998

Scheduling for Embedded Real-Time Systems.

Felice Balarin, Luciano Lavagno, Praveen K. Murthy, Alberto L. Sangiovanni-Vincentelli

IEEE Des. Test Comput., 1998

Priority Assignment for Embedded Reactive Real-Time Systems.

Felice Balarin

Proceedings of the Languages, 1998

Correctness of the Concurrent Approach to Symbolic Verification of Interleaved Models.

Felice Balarin

Proceedings of the Computer Aided Verification, 10th International Conference, 1998

1997

Verifying invariants by approximate image computation.

Felice Balarin

Proceedings of the Second International Workshop on Verification of Infinite State Systems, 1997

Schedule Validation for Embedded Reactive Real-Time Systems.

Felice Balarin, Alberto L. Sangiovanni-Vincentelli

Proceedings of the 34st Conference on Design Automation, 1997

Automatic Generation of a Real-Time Operating System for Embedded Systems.

Felice Balarin, Massimiliano Chiodo, Attila Jurecska, Luciano Lavagno, Bassam Tabbara, Alberto L. Sangiovanni-Vincentelli

Proceedings of the Fifth International Workshop on Hardware/Software Codesign, 1997

1996

Approximate reachability analysis of timed automata.

Felice Balarin

Proceedings of the 17th IEEE Real-Time Systems Symposium (RTSS '96), 1996

Formal Verification of Embedded Systems based on CFSM Networks.

Felice Balarin, Harry Hsieh, Attila Jurecska, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli

Proceedings of the 33st Conference on Design Automation, 1996

1995

An Iterative Approach to Verification of Real-Time Systems.

Felice Balarin, Alberto L. Sangiovanni-Vincentelli

Formal Methods Syst. Des., 1995

It Usually Works: The Temporal Logic of Stochastic Systems.

Adnan Aziz, Vigyan Singhal, Felice Balarin

Proceedings of the Computer Aided Verification, 1995

Supervisory Control of Finite State Machines.

Adnan Aziz, Felice Balarin, Robert K. Brayton, Marika Domenica Di Benedetto, Alexander Saldanha

Proceedings of the Computer Aided Verification, 1995

1994

Iterative algorithms for formal verification of embedded real-time systems.

Felice Balarin, Alberto L. Sangiovanni-Vincentelli

Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

HSIS: A BDD-Based Environment for Formal Verification.

Adnan Aziz, Felice Balarin, Szu-Tsung Cheng, Ramin Hojati, Timothy Kam, Sriram C. Krishnan, Rajeev K. Ranjan, Thomas R. Shiple, Vigyan Singhal, Serdar Tasiran, Huey-Yih Wang, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli

Proceedings of the 31st Conference on Design Automation, 1994

On the Automatic Computation of Network Invariants.

Felice Balarin, Alberto L. Sangiovanni-Vincentelli

Proceedings of the Computer Aided Verification, 6th International Conference, 1994

1993

Verilog HDL Modeling Styles for Formal Verification.

Felice Balarin, Gary York

Proceedings of the Computer Hardware Description Languages and their Applications, Proceedings of the 11th IFIP WG10.2 International Conference on Computer Hardware Description Languages and their Applications, 1993

An Iterative Approach to Language Containment.

Felice Balarin, Alberto L. Sangiovanni-Vincentelli

Proceedings of the Computer Aided Verification, 5th International Conference, 1993

1992

A Verification Strategy for Timing-Constrained Systems.

Felice Balarin, Alberto L. Sangiovanni-Vincentelli

Proceedings of the Computer Aided Verification, Fourth International Workshop, 1992