Yoshiyasu Doi

According to our database, Yoshiyasu Doi authored at least 15 papers between 2003 and 2018.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2018

Managing Non-Volatile Memory in Database Systems.

Alexander van Renen, Viktor Leis, Alfons Kemper, Thomas Neumann, Takushi Hashida, Kazuichi Oe, Yoshiyasu Doi, Lilian Harada, Mitsuru Sato

Proceedings of the 2018 International Conference on Management of Data, 2018

2014

A 56-Gb/s receiver front-end with a CTLE and 1-tap DFE in 20-nm CMOS.

Takayuki Shibasaki, Win Chaivipas, Yanfei Chen, Yoshiyasu Doi, Takayuki Hamada, Hideki Takauchi, Toshihiko Mori, Yoichi Koyanagi, Hirotaka Tamura

Proceedings of the Symposium on VLSI Circuits, 2014

2013

A 32 Gb/s Data-Interpolator Receiver With Two-Tap DFE Fabricated With 28-nm CMOS Process.

Yoshiyasu Doi, Takayuki Shibasaki, Takumi Danjo, Win Chaivipas, Takushi Hashida, Hiroki Miyaoka, Masanori Hoshino, Yoichi Koyanagi, Takuji Yamamoto, Sanroku Tsukamoto, Hirotaka Tamura

IEEE J. Solid State Circuits, 2013

32Gb/s data-interpolator receiver with 2-tap DFE in 28nm CMOS.

Yoshiyasu Doi, Takayuki Shibasaki, Takumi Danjo, Win Chaivipas, Takushi Hashida, Hiroki Miyaoka, Masanori Hoshino, Yoichi Koyanagi, Takuji Yamamoto, Sanroku Tsukamoto, Hirotaka Tamura

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2011

A 60-GHz Injection-Locked Frequency Divider Using Multi-Order <i>LC</i> Oscillator Topology for Wide Locking Range.

Keita Takatsu, Hirotaka Tamura, Takuji Yamamoto, Yoshiyasu Doi, Kouichi Kanda, Takayuki Shibasaki, Tadahiro Kuroda

IEICE Trans. Electron., 2011

2010

A 3 Watt 39.8-44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS.

Nikola Nedovic, Anders Kristensson, Samir Parikh, Subodh M. Reddy, Scott McLeod, Nestoras Tzartzanis, Kouichi Kanda, Takuji Yamamoto, Satoshi Matsubara, Masaya Kibune, Yoshiyasu Doi, Satoshi Ide, Yukito Tsunoda, Tetsuji Yamabana, Takayuki Shibasaki, Yasumoto Tomita, Takayuki Hamada, Mariko Sugawara, Tadashi Ikeuchi, Naoki Kuwata, Hirotaka Tamura, Junji Ogawa, William W. Walker

IEEE J. Solid State Circuits, 2010

A 5Gb/s transceiver with an ADC-based feedforward CDR and CMA adaptive equalizer in 65nm CMOS.

Hisakatsu Yamaguchi, Hirotaka Tamura, Yoshiyasu Doi, Yasumoto Tomita, Takayuki Hamada, Masaya Kibune, Shuhei Ohmoto, Keita Tateishi, Oleksiy Tyshchenko, Ali Sheikholeslami, Tomokazu Higuchi, Junji Ogawa, Tamio Saito, Hideki Ishida, Kohtaroh Gotoh

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

A 60-GHz 1.65mW 25.9% locking range multi-order LC oscillator based injection locked frequency divider in 65nm CMOS.

Keita Takatsu, Hirotaka Tamura, Takuji Yamamoto, Yoshiyasu Doi, Kouichi Kanda, Takayuki Shibasaki, Tadahiro Kuroda

Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009

A Zero-IF 60 GHz 65 nm CMOS Transceiver With Direct BPSK Modulation Demonstrating up to 6 Gb/s Data Rates Over a 2 m Wireless Link.

Alexander Tomkins, Ricardo Andres Aroca, Takuji Yamamoto, Sean T. Nicolson, Yoshiyasu Doi, Sorin P. Voinigescu

IEEE J. Solid State Circuits, 2009

A Single-40 Gb/s Dual-20 Gb/s Serializer IC With SFI-5.2 Interface in 65 nm CMOS.

Kouichi Kanda, Hirotaka Tamura, Takuji Yamamoto, Satoshi Matsubara, Masaya Kibune, Yoshiyasu Doi, Takayuki Shibasaki, Nestoras Tzartzanis, Anders Kristensson, Samir Parikh, Satoshi Ide, Yukito Tsunoda, Tetsuji Yamabana, Mariko Sugawara, Naoki Kuwata, Tadashi Ikeuchi, Junji Ogawa, William W. Walker

IEEE J. Solid State Circuits, 2009

A single-40Gb/s dual-20Gb/s serializer IC with SFI-5.2 interface in 65nm CMOS.

Kouichi Kanda, Hirotaka Tamura, Takuji Yamamoto, Satoshi Matsubara, Masaya Kibune, Yoshiyasu Doi, Takayuki Shibasaki, Nestoras Tzartzanis, Anders Kristensson, Samir Parikh, Satoshi Ide, Yukito Tsunoda, Tetsuji Yamabana, Mariko Sugawara, Naoki Kuwata, Tadashi Ikeuchi, Junji Ogawa, William W. Walker

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2008

A zero-IF 60GHz transceiver in 65nm CMOS with ≫ 3.5Gb/s links.

Alexander Tomkins, Ricardo Andres Aroca, Takuji Yamamoto, Sean T. Nicolson, Yoshiyasu Doi, Sorin P. Voinigescu

Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2005

A 5-6.4-Gb/s 12-channel transceiver with pre-emphasis and equalization.

Hirohito Higashi, Syunitirou Masaki, Masaya Kibune, Satoshi Matsubara, Takaya Chiba, Yoshiyasu Doi, Hisakatsu Yamaguchi, Hideki Takauchi, Hideki Ishida, Kohtaroh Gotoh, Hirotaka Tamura

IEEE J. Solid State Circuits, 2005

A 0.8-1.3V 16-channel 2.5Gb/s high-speed serial transceiver in a 90nm standard CMOS process.

Yoshiyasu Doi, Syunitirou Masaki, Takaya Chiba, Hirohito Higashi, Hisakatsu Yamaguchi, Hideki Takauchi, Hideki Ishida, Kohtaroh Gotoh, Junji Ogawa, Hirotaka Tamura

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2003

A CMOS multichannel 10-Gb/s transceiver.

Hideki Takauchi, Hirotaka Tamura, Satoshi Matsubara, Masaya Kibune, Yoshiyasu Doi, Takaya Chiba, Hideaki Anbutsu, Hisakatsu Yamaguchi, Toshihiko Mori, Motomu Takatsu, Kohtaroh Gotoh, Toshiaki Sakai, Takeshi Yamamura

IEEE J. Solid State Circuits, 2003