Hiroyuki Usui
Orcid: 0000-0002-2447-5372
According to our database1,
Hiroyuki Usui
authored at least 17 papers
between 2008 and 2023.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2023
Automatic measurement of building setbacks and streetscape widths and their spatial variability along streets and in plots: integration of streetscape skeletons and plot geometry.
Int. J. Geogr. Inf. Sci., April, 2023
Simulation of urban perforation after random vacant plot generation: application of the thinning point process.
Int. J. Geogr. Inf. Sci., 2023
2022
A normative model to estimate the number of persons not social distancing in a 3D complex built space.
Int. J. Geogr. Inf. Sci., 2022
2020
A comparison of neighbourhood relations based on ordinary Delaunay diagrams and area Delaunay diagrams: an application to define the neighbourhood relations of buildings.
Int. J. Geogr. Inf. Sci., 2020
Variography and Morphometry for Classifying Building Centroids: Protocol, Data and Script.
Proceedings of the Computational Science and Its Applications - ICCSA 2020, 2020
2019
A bottom-up approach for delineating urban areas minimizing the connection cost of built clusters: Comparison with top-down-based densely inhabited districts.
Comput. Environ. Urban Syst., 2019
2018
Estimation of geometric route distance from its topological distance: application to narrow road networks in Tokyo.
J. Geogr. Syst., 2018
Statistical distribution of building lot frontage: application for Tokyo downtown districts.
J. Geogr. Syst., 2018
Size distribution of urban blocks in the Tokyo Metropolitan Region: estimation by urban block density and road width on the basis of normative plane tessellation.
Int. J. Geogr. Inf. Sci., 2018
2016
DASH: Deadline-Aware High-Performance Memory Scheduler for Heterogeneous Systems with Hardware Accelerators.
ACM Trans. Archit. Code Optim., 2016
2015
SQUASH: Simple QoS-Aware High-Performance Memory Scheduler for Heterogeneous Systems with Hardware Accelerators.
CoRR, 2015
2014
IEICE Trans. Electron., 2014
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
2013
Proceedings of the Design, Automation and Test in Europe, 2013
Proceedings of the Design, Automation and Test in Europe, 2013
2012
A low power many-core SoC with two 32-core clusters connected by tree based NoC for multimedia applications.
Proceedings of the Symposium on VLSI Circuits, 2012
2008
A 9.7mW AAC-Decoding, 620mW H.264 720p 60fps Decoding, 8-Core Media Processor with Embedded Forward-Body-Biasing and Power-Gating Circuit in 65nm CMOS Technology.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008