Jun Tanabe

Orcid: 0009-0005-1417-7151

According to our database1, Jun Tanabe authored at least 13 papers between 2005 and 2023.

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Bibliography

2023
Adaptive Background Music According to the Player's Arousal for DareFightingICE.
Proceedings of the 13th International Conference on Advances in Information Technology, 2023

Minecraft Video Aesthetics Quality Assessment Model.
Proceedings of the 13th International Conference on Advances in Information Technology, 2023

2020
A 20.5 TOPS Multicore SoC With DNN Accelerator and Image Signal Processor for Automotive Applications.
IEEE J. Solid State Circuits, 2020

2019
A 20.5TOPS and 217.3GOPS/mm<sup>2</sup> Multicore SoC with DNN Accelerator and Image Signal Processor Complying with ISO26262 for Automotive Applications.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2015
18.2 A 1.9TOPS and 564GOPS/W heterogeneous multicore SoC with color-based object classification accelerator for image-recognition applications.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014
Architecture and Evaluation of Low Power Many-Core SoC with Two 32-Core Clusters.
IEICE Trans. Electron., 2014

An evaluation of an energy efficient many-core SoC with parallelized face detection.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
Development of low power many-core SoC for multimedia applications.
Proceedings of the Design, Automation and Test in Europe, 2013

A near-future prediction method for low power consumption on a many-core processor.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
A low power many-core SoC with two 32-core clusters connected by tree based NoC for multimedia applications.
Proceedings of the Symposium on VLSI Circuits, 2012

2009
Empirical Analysis of Travel Time Reliability Measures in Hanshin Expressway Network.
J. Intell. Transp. Syst., 2009

2008
A 9.7mW AAC-Decoding, 620mW H.264 720p 60fps Decoding, 8-Core Media Processor with Embedded Forward-Body-Biasing and Power-Gating Circuit in 65nm CMOS Technology.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2005
Development of Image Recognition Processor Based on Configurable Processor.
J. Robotics Mechatronics, 2005


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