Hoki Kim

Orcid: 0000-0001-5361-459X

According to our database1, Hoki Kim authored at least 20 papers between 2001 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Fair Sampling in Diffusion Models through Switching Mechanism.
CoRR, 2024

Fair Sampling in Diffusion Models through Switching Mechanism.
Proceedings of the Thirty-Eighth AAAI Conference on Artificial Intelligence, 2024

2023
Bridged adversarial training.
Neural Networks, October, 2023

Fast sharpness-aware training for periodic time series classification and forecasting.
Appl. Soft Comput., September, 2023

Generating Transferable Adversarial Examples for Speech Classification.
Pattern Recognit., May, 2023

GradDiv: Adversarial Robustness of Randomized Neural Networks via Gradient Diversity Regularization.
IEEE Trans. Pattern Anal. Mach. Intell., 2023

Exploring the Effect of Multi-step Ascent in Sharpness-Aware Minimization.
CoRR, 2023

Stability Analysis of Sharpness-Aware Minimization.
CoRR, 2023

Exploring Diverse Feature Extractions for Adversarial Audio Detection.
IEEE Access, 2023

Fantastic Robustness Measures: The Secrets of Robust Generalization.
Proceedings of the Advances in Neural Information Processing Systems 36: Annual Conference on Neural Information Processing Systems 2023, 2023

Differentially Private Sharpness-Aware Training.
Proceedings of the International Conference on Machine Learning, 2023

2022
Variational cycle-consistent imputation adversarial networks for general missing patterns.
Pattern Recognit., 2022

Comment on Transferability and Input Transformation with Additive Noise.
CoRR, 2022

2021
Compact class-conditional domain invariant learning for multi-class domain adaptation.
Pattern Recognit., 2021

Understanding Catastrophic Overfitting in Single-step Adversarial Training.
Proceedings of the Thirty-Fifth AAAI Conference on Artificial Intelligence, 2021

2020
Torchattacks : A Pytorch Repository for Adversarial Attacks.
CoRR, 2020

2008
A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier.
IEEE J. Solid State Circuits, 2008

2007
A 500MHz Random Cycle 1.5ns-Latency, SOI Embedded DRAM Macro Featuring a 3T Micro Sense Amplifier.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2005
An 800-MHz embedded DRAM with a concurrent refresh mode.
IEEE J. Solid State Circuits, 2005

2001
A practical built-in current sensor for I_DDQ testing.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001


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