Hoki Kim
Orcid: 0000-0001-5361-459X
According to our database1,
Hoki Kim authored at least 33 papers
between 2001 and 2026.
Collaborative distances:
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Bibliography
2026
IEEE Trans. Ind. Informatics, June, 2026
CoRR, May, 2026
IEEE Access, 2026
2025
Int. J. Inf. Sec., June, 2025
Inf. Sci., 2025
Black-box adversarial examples via frequency distortion against fault diagnosis systems.
Appl. Soft Comput., 2025
IEEE Access, 2025
Proceedings of the Advances in Neural Information Processing Systems 38: Annual Conference on Neural Information Processing Systems 2025, 2025
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition Workshops, 2025
2024
J. Ambient Intell. Humaniz. Comput., August, 2024
Evaluating practical adversarial robustness of fault diagnosis systems via spectrogram-aware ensemble method.
Eng. Appl. Artif. Intell., 2024
Proceedings of the Advances in Neural Information Processing Systems 37: Annual Conference on Neural Information Processing Systems 2024, 2024
Proceedings of the Thirty-Eighth AAAI Conference on Artificial Intelligence, 2024
2023
Fast sharpness-aware training for periodic time series classification and forecasting.
Appl. Soft Comput., September, 2023
Pattern Recognit., May, 2023
GradDiv: Adversarial Robustness of Randomized Neural Networks via Gradient Diversity Regularization.
IEEE Trans. Pattern Anal. Mach. Intell., 2023
IEEE Access, 2023
Proceedings of the Advances in Neural Information Processing Systems 36: Annual Conference on Neural Information Processing Systems 2023, 2023
Proceedings of the International Conference on Machine Learning, 2023
2022
Variational cycle-consistent imputation adversarial networks for general missing patterns.
Pattern Recognit., 2022
2021
Compact class-conditional domain invariant learning for multi-class domain adaptation.
Pattern Recognit., 2021
Proceedings of the Thirty-Fifth AAAI Conference on Artificial Intelligence, 2021
2020
2008
A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier.
IEEE J. Solid State Circuits, 2008
2007
A 500MHz Random Cycle 1.5ns-Latency, SOI Embedded DRAM Macro Featuring a 3T Micro Sense Amplifier.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
2005
IEEE J. Solid State Circuits, 2005
2001
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001