Hillery C. Hunter

According to our database1, Hillery C. Hunter authored at least 20 papers between 2000 and 2020.

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Bibliography

2020
Temperature Aware Adaptations for Improved Read Reliability in STT-MRAM Memory Subsystem.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

2019
BlueConnect: Decomposing all-reduce for deep learning on heterogeneous network hierarchy.
IBM J. Res. Dev., 2019

BlueConnect: Decomposing All-Reduce for Deep Learning on Heterogeneous Network Hierarchy.
Proceedings of Machine Learning and Systems 2019, 2019

2018
PANEL: Open panel and discussion on tackling complexity, reproducibility and tech transfer challenges in a rapidly evolving AI/ML/systems research.
Proceedings of the 1st on Reproducible Quality-Efficient Systems Tournament on Co-designing Pareto-efficient Deep Learning, 2018

2015
Guest Editorial Computing in Emerging Technologies (Second Issue).
IEEE J. Emerg. Sel. Topics Circuits Syst., 2015

2014
Guest Editorial Computing in Emerging Technologies (First Issue).
IEEE J. Emerg. Sel. Topics Circuits Syst., 2014

Adapting Server Systems for New Memory Technologies.
Computer, 2014

2013
Understanding and mitigating refresh overheads in high-density DDR4 DRAM systems.
Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013

2011
Coordinating DRAM and Last-Level-Cache Policies with the Virtual Write Queue.
IEEE Micro, 2011

2010
Elastic Refresh: Techniques to Mitigate Refresh Penalties in High Density Memory.
Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010

The virtual write queue: coordinating DRAM and last-level cache policies.
Proceedings of the 37th International Symposium on Computer Architecture (ISCA 2010), 2010

2009
Hardware-compiler co-design for adjustable data power savings.
Microprocess. Microsystems, 2009

A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS.
IEEE J. Solid State Circuits, 2009

2008
A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier.
IEEE J. Solid State Circuits, 2008

2007
A 500MHz Random Cycle 1.5ns-Latency, SOI Embedded DRAM Macro Featuring a 3T Micro Sense Amplifier.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2003
An innovative low-power high-performance programmable signal processor for digital communications.
IBM J. Res. Dev., 2003

A new look at exploiting data parallelism in embedded systems.
Proceedings of the International Conference on Compilers, 2003

2002
Code coverage and input variability: effects on architecture and compiler research.
Proceedings of the International Conference on Compilers, 2002

2001
Enhancing loop buffering of media and telecommunications applications using low-overhead predication.
Proceedings of the 34th Annual International Symposium on Microarchitecture, 2001

2000
Hardware Support for Dynamic Management of Compiler-Directed Computation Reuse.
Proceedings of the ASPLOS-IX Proceedings of the 9th International Conference on Architectural Support for Programming Languages and Operating Systems, 2000


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