Stanley Schuster

According to our database1, Stanley Schuster authored at least 12 papers between 2000 and 2009.

Collaborative distances:

Awards

IEEE Fellow

IEEE Fellow 1990, "For contributions to high-performance static random access memory design.".

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2009
Fast Low Power eDRAM Hierarchical Differential Sense Amplifier.
IEEE J. Solid State Circuits, 2009

2008
A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier.
IEEE J. Solid State Circuits, 2008

2007
A 500MHz Random Cycle 1.5ns-Latency, SOI Embedded DRAM Macro Featuring a 3T Micro Sense Amplifier.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2005
Logic-based eDRAM: Origins and rationale for use.
IBM J. Res. Dev., 2005

2003
Dynamically Tuning Processor Resources with Adaptive Processing.
Computer, 2003

2002
Early-Stage Definition of LPX: A Low Power Issue-Execute Processor.
Proceedings of the Power-Aware Computer Systems, Second International Workshop, 2002

Tradeoffs in power-efficient issue queue design.
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

Synchronous Interlocked Pipelines.
Proceedings of the 8th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2002), 2002

2001
A circuit level implementation of an adaptive issue queue for power-aware microprocessors.
Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, 2001

2000
Power-Aware Microarchitecture: Design and Modeling Challenges for Next-Generation Microprocessors.
IEEE Micro, 2000

Design and characteristics of n-channel insulated-gate field-effect transistors.
IBM J. Res. Dev., 2000

An Adaptive Issue Queue for Reduced Power at High Performance.
Proceedings of the Power-Aware Computer Systems, First International Workshop, 2000


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