Hoonki Kim
Orcid: 0000-0003-0720-6821
According to our database1,
Hoonki Kim
authored at least 11 papers
between 2017 and 2023.
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Bibliography
2023
Breakthrough Design Technology Co-optimization using BSPDN and Standard Cell Variants for Maximizing Block-level PPA.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
2022
A 3-nm Gate-All-Around SRAM Featuring an Adaptive Dual-Bitline and an Adaptive Cell-Power Assist Circuit.
IEEE J. Solid State Circuits, 2022
3nm Gate-All-Around (GAA) Design-Technology Co-Optimization (DTCO) for succeeding PPA by Technology.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022
2021
A Wide-Range Static Current-Free Current Mirror-Based LS With Logic Error Detection for Near-Threshold Operation.
IEEE J. Solid State Circuits, 2021
24.3 A 3nm Gate-All-Around SRAM Featuring an Adaptive Dual-BL and an Adaptive Cell-Power Assist Circuit.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
2020
IEEE Access, 2020
2019
Bitline Charge-Recycling SRAM Write Assist Circuitry for $V_{\mathrm{MIN}}$ Improvement and Energy Saving.
IEEE J. Solid State Circuits, 2019
2018
Half-and-Half Compare Content Addressable Memory with Charge-Sharing Based Selective Match-Line Precharge Scheme.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
A 7nm FinFET SRAM using EUV lithography with dual write-driver-assist circuitry for low-voltage applications.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
2017
A 10 nm FinFET 128 Mb SRAM With Assist Adjustment System for Power, Performance, and Area Optimization.
IEEE J. Solid State Circuits, 2017
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017